Memory design using one-transistor gain cell on SOI

Takashi Ohsawa, Katsuyuki Fujita, Tomoki Higashi, Yoshihisa Iwata, Takeshi Kajiyama, Yoshiaki Asao, Kazumasa Sunouchi

    Research output: Contribution to journalConference articlepeer-review

    36 Citations (Scopus)

    Abstract

    Memory design was carried out using one-transistor gain cell on SOI. This memory design is based on a one-transistor gain cell which is smaller, less complex to make and more scalable to sub-0.1μm generations than the existing dynamic random access memory (DRAM) cells, without resorting to new materials and device structure. Transient analysis of a device simulation was also discussed to verify operation of the floating body transistor cell (FBC).

    Original languageEnglish
    Pages (from-to)152-153+454+151
    JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    Publication statusPublished - 2002 Jan 1
    Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
    Duration: 2002 Feb 32002 Feb 7

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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