Measurement of local residual stress in Si chips mounted by flip chip technology using micron scale strain sensors

Takuya Sasaki, Nobuki Ueta, Hideo Miura

Research output: Contribution to journalArticlepeer-review

Abstract

The change of the electronic performance of NMOS transistors caused by mechanical stress was measured by applying a four-point bending method. The change rate of the transconductance of NMOS transistors increased to about 15%/100-MPa by decreasing the gate length from 400 nm to 150 nm. In addition, the local residual stress in the stacked chips mounted by a flip chip technology was measured by utilizing piezoresistive stress sensors with 2-μm long gauges. The amplitude of the residual stress in the top chip was almost constant of about 220 MPa regardless of the bottom bump alignment. On the other hand, the amplitude of the residual stress in the bottom chip decreased to about 80 MPa depending on the relative position of bumps between the top and bottom chips.

Original languageEnglish
Pages (from-to)831-838
Number of pages8
JournalNihon Kikai Gakkai Ronbunshu, A Hen/Transactions of the Japan Society of Mechanical Engineers, Part A
Volume75
Issue number755
DOIs
Publication statusPublished - 2009 Jul

Keywords

  • 3-D stacked structure
  • Experimental mechanics
  • Flip-chip technology
  • Residual stress
  • Structural reliability

ASJC Scopus subject areas

  • Materials Science(all)
  • Mechanics of Materials
  • Mechanical Engineering

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