Lowest variability SOI FinFETs having multiple Vt by back-biasing

T. Matsukawa, K. Fukuda, Y. X. Liu, K. Endo, J. Tsukada, H. Yamauchi, Y. Ishikawa, S. O'Uchi, W. Mizubayashi, S. Migita, Y. Morita, H. Ota, M. Masahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479933310
DOIs
Publication statusPublished - 2014 Sep 8
Externally publishedYes
Event34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States
Duration: 2014 Jun 92014 Jun 12

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other34th Symposium on VLSI Technology, VLSIT 2014
CountryUnited States
CityHonolulu
Period14/6/914/6/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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