Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

Hiroyuki Nakase; Tsuyoshi Sagitani; Kazuya Masu; Kazuo Tsubouchi

Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

Hiroyuki Nakase, Tsuyoshi Sagitani, Kazuya Masu, Kazuo Tsubouchi

ENG - Institute of Engineering Education

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

We have proposed a theoretical design method for the lower boundary of supply voltage using the universal E_b/N₀-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10^-10 with the conditions of 10 years term, 10 GHz clock and 10⁶ gate, the bit error rate of a gate should be less than 10^-34. For a BER of 10^-34 V_DD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, V_DD should be larger than 0.2V under the ideal thermal noise environment. The measured E _b/N₀-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

Original language	English
Journal	Japanese Journal of Applied Physics, Part 2: Letters
Volume	42
Issue number	10 A
Publication status	Published - 2003 Oct 1

Keywords

CMOS LSI
E/N characteristics
Lower boundary of supply voltage

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy (miscellaneous)
Physics and Astronomy(all)

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title = "Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory",

abstract = "We have proposed a theoretical design method for the lower boundary of supply voltage using the universal Eb/N0-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10-10 with the conditions of 10 years term, 10 GHz clock and 106 gate, the bit error rate of a gate should be less than 10-34. For a BER of 10-34 VDD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, VDD should be larger than 0.2V under the ideal thermal noise environment. The measured E b/N0-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.",

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TY - JOUR

T1 - Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

AU - Nakase, Hiroyuki

AU - Sagitani, Tsuyoshi

AU - Masu, Kazuya

AU - Tsubouchi, Kazuo

PY - 2003/10/1

Y1 - 2003/10/1

N2 - We have proposed a theoretical design method for the lower boundary of supply voltage using the universal Eb/N0-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10-10 with the conditions of 10 years term, 10 GHz clock and 106 gate, the bit error rate of a gate should be less than 10-34. For a BER of 10-34 VDD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, VDD should be larger than 0.2V under the ideal thermal noise environment. The measured E b/N0-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

AB - We have proposed a theoretical design method for the lower boundary of supply voltage using the universal Eb/N0-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10-10 with the conditions of 10 years term, 10 GHz clock and 106 gate, the bit error rate of a gate should be less than 10-34. For a BER of 10-34 VDD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, VDD should be larger than 0.2V under the ideal thermal noise environment. The measured E b/N0-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

KW - CMOS LSI

KW - E/N characteristics

KW - Lower boundary of supply voltage

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