Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

Hiroyuki Nakase; Tsuyoshi Sagitani; Kazuya Masu; Kazuo Tsubouchi

Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

Hiroyuki Nakase, Tsuyoshi Sagitani, Kazuya Masu, Kazuo Tsubouchi

Research output: Contribution to journal › Article › peer-review

Abstract

We have proposed a theoretical design method for the lower boundary of supply voltage using the universal E_b/N₀-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10^-10 with the conditions of 10 years term, 10 GHz clock and 10⁶ gate, the bit error rate of a gate should be less than 10^-34. For a BER of 10^-34 V_DD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, V_DD should be larger than 0.2V under the ideal thermal noise environment. The measured E _b/N₀-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

Original language	English
Journal	Japanese Journal of Applied Physics, Part 2: Letters
Volume	42
Issue number	10 A
Publication status	Published - 2003 Oct 1
Externally published	Yes

Keywords

CMOS LSI
E/N characteristics
Lower boundary of supply voltage

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy (miscellaneous)
Physics and Astronomy(all)

Cite this

@article{e2f3cbbe15fb4ecaa498306a026cce37,

title = "Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory",

abstract = "We have proposed a theoretical design method for the lower boundary of supply voltage using the universal Eb/N0-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10-10 with the conditions of 10 years term, 10 GHz clock and 106 gate, the bit error rate of a gate should be less than 10-34. For a BER of 10-34 VDD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, VDD should be larger than 0.2V under the ideal thermal noise environment. The measured E b/N0-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.",

keywords = "CMOS LSI, E/N characteristics, Lower boundary of supply voltage",

author = "Hiroyuki Nakase and Tsuyoshi Sagitani and Kazuya Masu and Kazuo Tsubouchi",

year = "2003",

month = oct,

day = "1",

language = "English",

volume = "42",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "10 A",

}

TY - JOUR

T1 - Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

AU - Nakase, Hiroyuki

AU - Sagitani, Tsuyoshi

AU - Masu, Kazuya

AU - Tsubouchi, Kazuo

PY - 2003/10/1

Y1 - 2003/10/1

N2 - We have proposed a theoretical design method for the lower boundary of supply voltage using the universal Eb/N0-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10-10 with the conditions of 10 years term, 10 GHz clock and 106 gate, the bit error rate of a gate should be less than 10-34. For a BER of 10-34 VDD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, VDD should be larger than 0.2V under the ideal thermal noise environment. The measured E b/N0-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

AB - We have proposed a theoretical design method for the lower boundary of supply voltage using the universal Eb/N0-bit error rate (BER) characteristics from the system viewpoint. In order to achieve the system error rate of less than 10-10 with the conditions of 10 years term, 10 GHz clock and 106 gate, the bit error rate of a gate should be less than 10-34. For a BER of 10-34 VDD should be larger than 0.1 V for 0.13 μm complementally metal-oxide-silicon (CMOS) LSI. For 0.05 μm CMOS of next generation, VDD should be larger than 0.2V under the ideal thermal noise environment. The measured E b/N0-BER characteristics of CMOS circuits as a function of supply voltage have agree well with the theoretical value.

KW - CMOS LSI

KW - E/N characteristics

KW - Lower boundary of supply voltage

UR - http://www.scopus.com/inward/record.url?scp=0344083343&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0344083343&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0344083343

VL - 42

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 10 A

ER -

Lower Boundary of Supply Voltage in Digital ULSI Based on the Communication Theory

Abstract

Keywords

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this