Low Vt Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases

H. Y. Yu; S. Z. Chang; A. Veloso; A. Lauwers; C. Adelmann; B. Onsia; S. Van Elshocht; R. Singanamalla; M. Demand; R. Vos; T. Kauerauf; S. Brus; X. Shi; S. Kubicek; C. Vrancken; R. Mitsuhashi; P. Lehnen; J. Kittl; M. Niwa; K. M. Yin; T. Hoffmann; S. Degendt; M. Jurczak; P. Absil; S. Biesemans

doi:10.1109/VLSIT.2007.4339710

Low V_t Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases

H. Y. Yu, S. Z. Chang, A. Veloso, A. Lauwers, C. Adelmann, B. Onsia, S. Van Elshocht, R. Singanamalla, M. Demand, R. Vos, T. Kauerauf, S. Brus, X. Shi, S. Kubicek, C. Vrancken, R. Mitsuhashi, P. Lehnen, J. Kittl, M. Niwa, K. M. YinT. Hoffmann, S. Degendt, M. Jurczak, P. Absil, S. Biesemans

Research output: Contribution to journal › Conference article › peer-review

19 Citations (Scopus)

Abstract

This paper reports a novel approach to implement low V_t Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5Å) can lower the NiSi FUSI nFET V_t by 300mV/500mV on HfSiON/SiON (resulting in a V_t.lin of 0.25V/0.18V respectively), w/o compromising the T_inv (<1Å variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower V_t, greatly-improved PBTI and 150x lower J_g wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low V_t CMOS using either dual phase (NiSi, Ni₃₂Si₁₂) or single phase (Ni₂Si) FUSI gate for both n- and pFETs.

Original language	English
Article number	4339710
Pages (from-to)	18-19
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2007.4339710
Publication status	Published - 2007 Dec 1
Externally published	Yes
Event	2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan Duration: 2007 Jun 12 → 2007 Jun 14

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/VLSIT.2007.4339710

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Yu, H. Y., Chang, S. Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Van Elshocht, S., Singanamalla, R., Demand, M., Vos, R., Kauerauf, T., Brus, S., Shi, X., Kubicek, S., Vrancken, C., Mitsuhashi, R., Lehnen, P., Kittl, J., Niwa, M., ... Biesemans, S. (2007). Low V_t Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases. Digest of Technical Papers - Symposium on VLSI Technology, 18-19. [4339710]. https://doi.org/10.1109/VLSIT.2007.4339710

Yu, HY, Chang, SZ, Veloso, A, Lauwers, A, Adelmann, C, Onsia, B, Van Elshocht, S, Singanamalla, R, Demand, M, Vos, R, Kauerauf, T, Brus, S, Shi, X, Kubicek, S, Vrancken, C, Mitsuhashi, R, Lehnen, P, Kittl, J, Niwa, M, Yin, KM, Hoffmann, T, Degendt, S, Jurczak, M, Absil, P & Biesemans, S 2007, 'Low V_t Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases', Digest of Technical Papers - Symposium on VLSI Technology, pp. 18-19. https://doi.org/10.1109/VLSIT.2007.4339710

@article{2839abfe98c14fee9ad0623d2a4ecd0e,

title = "Low Vt Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases",

abstract = "This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5{\AA}) can lower the NiSi FUSI nFET Vt by 300mV/500mV on HfSiON/SiON (resulting in a Vt.lin of 0.25V/0.18V respectively), w/o compromising the Tinv (<1{\AA} variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150x lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n- and pFETs.",

author = "Yu, {H. Y.} and Chang, {S. Z.} and A. Veloso and A. Lauwers and C. Adelmann and B. Onsia and {Van Elshocht}, S. and R. Singanamalla and M. Demand and R. Vos and T. Kauerauf and S. Brus and X. Shi and S. Kubicek and C. Vrancken and R. Mitsuhashi and P. Lehnen and J. Kittl and M. Niwa and Yin, {K. M.} and T. Hoffmann and S. Degendt and M. Jurczak and P. Absil and S. Biesemans",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/VLSIT.2007.4339710",

language = "English",

pages = "18--19",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

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note = "2007 Symposium on VLSI Technology, VLSIT 2007 ; Conference date: 12-06-2007 Through 14-06-2007",

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T1 - Low Vt Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases

AU - Yu, H. Y.

AU - Chang, S. Z.

AU - Veloso, A.

AU - Lauwers, A.

AU - Adelmann, C.

AU - Onsia, B.

AU - Van Elshocht, S.

AU - Singanamalla, R.

AU - Demand, M.

AU - Vos, R.

AU - Kauerauf, T.

AU - Brus, S.

AU - Shi, X.

AU - Kubicek, S.

AU - Vrancken, C.

AU - Mitsuhashi, R.

AU - Lehnen, P.

AU - Kittl, J.

AU - Niwa, M.

AU - Yin, K. M.

AU - Hoffmann, T.

AU - Degendt, S.

AU - Jurczak, M.

AU - Absil, P.

AU - Biesemans, S.

PY - 2007/12/1

Y1 - 2007/12/1

N2 - This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5Å) can lower the NiSi FUSI nFET Vt by 300mV/500mV on HfSiON/SiON (resulting in a Vt.lin of 0.25V/0.18V respectively), w/o compromising the Tinv (<1Å variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150x lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n- and pFETs.

AB - This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5Å) can lower the NiSi FUSI nFET Vt by 300mV/500mV on HfSiON/SiON (resulting in a Vt.lin of 0.25V/0.18V respectively), w/o compromising the Tinv (<1Å variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150x lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n- and pFETs.

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SN - 0743-1562

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JO - Digest of Technical Papers - Symposium on VLSI Technology

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M1 - 4339710

T2 - 2007 Symposium on VLSI Technology, VLSIT 2007

Y2 - 12 June 2007 through 14 June 2007

ER -

Low V_t Ni-FUSI CMOS technology using a DyO cap layer with either single or dual Ni-phases

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