This paper reports a novel approach to implement low Vt Ni-FUSI bulk CMOS by using a Dysprosium Oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5Å) can lower the NiSi FUSI nFET Vt by 300mV/500mV on HfSiON/SiON (resulting in a Vt.lin of 0.25V/0.18V respectively), w/o compromising the Tinv (<1Å variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150x lower Jg wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low Vt CMOS using either dual phase (NiSi, Ni32Si12) or single phase (Ni2Si) FUSI gate for both n- and pFETs.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 2007 Dec 1|
|Event||2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan|
Duration: 2007 Jun 12 → 2007 Jun 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering