Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion

Kousei Kumahara, Rui Liang, Sungho Lee, Yuki Miwa, Mariappan Murugesan, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD® to deposit a TSV liner SiO2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO2. In addition, solid-solid inter-diffusion bonding of 3-μm-thick Sn with 0.5-μm-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190°C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.

Original languageEnglish
Title of host publicationProceedings - IEEE 70th Electronic Components and Technology Conference, ECTC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1199-1204
Number of pages6
ISBN (Electronic)9781728161808
DOIs
Publication statusPublished - 2020 Jun
Event70th IEEE Electronic Components and Technology Conference, ECTC 2020 - Orlando, United States
Duration: 2020 Jun 32020 Jun 30

Publication series

NameProceedings - Electronic Components and Technology Conference
Volume2020-June
ISSN (Print)0569-5503

Conference

Conference70th IEEE Electronic Components and Technology Conference, ECTC 2020
CountryUnited States
CityOrlando
Period20/6/320/6/30

Keywords

  • Low-temperature bonding
  • Multichip-to-wafer 3D integration
  • Room-temperature CVD
  • TSV
  • via-last TSV

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion'. Together they form a unique fingerprint.

Cite this