Low temperature atomically flattening of Si surface of shallow trench isolation pattern

T. Goto, R. Kuroda, T. Suwa, A. Teramoto, N. Akagawa, D. Kimoto, S. Sugawa, T. Ohmi, Y. Kamata, Y. Kumagai, K. Shibusawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Low temperature (800 °C-900 °C) Ar annealing for atomically flattening was applied to shallow trench isolation (STI)-patterned wafers where Si and SiO2 coexist on the wafer surface. During the Ar annealing, concentrations of H2O and O2 residual gases in the annealing ambience was maintained at low level less than 30 ppb. Such low temperature and clean Ar ambience can suppress oxidation and etching of Si surface as well as a decomposition of thick SiO2 film for device isolation. As a result, the atomically flat Si surface was obtained for the Si active pattern having STI edge by the Ar annealing at 800 °C-900 °C. Owing to the introduction of the atomically flat Si/gate oxide interface, breakdown characteristic of the fabricated MOS capacitors was improved for the atomically flat devices.

Original languageEnglish
Title of host publicationAdvanced CMOS-Compatible Semiconductor Devices 17
EditorsS. Selberherr, Y. Omura, J. A. Martino, J. P. Raskin, H. Ishii, F. Gamiz, B. Y. Nguyen
PublisherElectrochemical Society Inc.
Pages285-292
Number of pages8
Edition5
ISBN (Electronic)9781607685395
DOIs
Publication statusPublished - 2015
EventSymposium on Advanced CMOS-Compatible Semiconductor Devices 17 - 227th ECS Meeting - Chicago, United States
Duration: 2015 May 242015 May 28

Publication series

NameECS Transactions
Number5
Volume66
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherSymposium on Advanced CMOS-Compatible Semiconductor Devices 17 - 227th ECS Meeting
CountryUnited States
CityChicago
Period15/5/2415/5/28

ASJC Scopus subject areas

  • Engineering(all)

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