Abstract
We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor (MNS) FET technology having conventional plane gate structure featuring fully low-temperature processing. The gate stack consists of directly grown Silicon Nitride (Si3N4) dielectric using high-density plasma and bcc-phase Tantalum (∼15μΩcm) / Tantalum Nitride (bcc-Ta/TaNx) stacked metal gate below 1.0ohm/sq. In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy (SPE) method. In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric (FDSOI) metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C.
| Original language | English |
|---|---|
| Pages | 67-68 |
| Number of pages | 2 |
| Publication status | Published - 2001 Jan 1 |
| Event | 2001 VLSI Technology Symposium - Kyoto, Japan Duration: 2001 Jun 12 → 2001 Jun 14 |
Other
| Other | 2001 VLSI Technology Symposium |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 01/6/12 → 01/6/14 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Shimada, H., Ohshima, I., Nakao, S. I., Nakagawa, M., Kanemoto, K., Hirayama, M., Sugawa, S., & Ohmi, T. (2001). Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C. 67-68. Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.