Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C

H. Shimada; I. Ohshima; S. I. Nakao; M. Nakagawa; K. Kanemoto; M. Hirayama; S. Sugawa; T. Ohmi

Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C

H. Shimada, I. Ohshima, S. I. Nakao, M. Nakagawa, K. Kanemoto, M. Hirayama, S. Sugawa, T. Ohmi

Research output: Contribution to conference › Paper › peer-review

Abstract

We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor (MNS) FET technology having conventional plane gate structure featuring fully low-temperature processing. The gate stack consists of directly grown Silicon Nitride (Si₃N₄) dielectric using high-density plasma and bcc-phase Tantalum (∼15μΩcm) / Tantalum Nitride (bcc-Ta/TaNx) stacked metal gate below 1.0ohm/sq. In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy (SPE) method. In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric (FDSOI) metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C.

Original language	English
Pages	67-68
Number of pages	2
Publication status	Published - 2001 Jan 1
Event	2001 VLSI Technology Symposium - Kyoto, Japan Duration: 2001 Jun 12 → 2001 Jun 14

Other

Other	2001 VLSI Technology Symposium
Country/Territory	Japan
City	Kyoto
Period	01/6/12 → 01/6/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C. / Shimada, H.; Ohshima, I.; Nakao, S. I.; Nakagawa, M.; Kanemoto, K.; Hirayama, M.; Sugawa, S.; Ohmi, T.

2001. 67-68 Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.

Research output: Contribution to conference › Paper › peer-review

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title = "Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C",

abstract = "We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor (MNS) FET technology having conventional plane gate structure featuring fully low-temperature processing. The gate stack consists of directly grown Silicon Nitride (Si3N4) dielectric using high-density plasma and bcc-phase Tantalum (∼15μΩcm) / Tantalum Nitride (bcc-Ta/TaNx) stacked metal gate below 1.0ohm/sq. In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy (SPE) method. In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric (FDSOI) metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C.",

author = "H. Shimada and I. Ohshima and Nakao, {S. I.} and M. Nakagawa and K. Kanemoto and M. Hirayama and S. Sugawa and T. Ohmi",

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AU - Shimada, H.

AU - Ohshima, I.

AU - Nakao, S. I.

AU - Nakagawa, M.

AU - Kanemoto, K.

AU - Hirayama, M.

AU - Sugawa, S.

AU - Ohmi, T.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor (MNS) FET technology having conventional plane gate structure featuring fully low-temperature processing. The gate stack consists of directly grown Silicon Nitride (Si3N4) dielectric using high-density plasma and bcc-phase Tantalum (∼15μΩcm) / Tantalum Nitride (bcc-Ta/TaNx) stacked metal gate below 1.0ohm/sq. In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy (SPE) method. In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric (FDSOI) metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C.

AB - We have developed a low-resistivity metal gate Metal-Nitride-Semiconductor (MNS) FET technology having conventional plane gate structure featuring fully low-temperature processing. The gate stack consists of directly grown Silicon Nitride (Si3N4) dielectric using high-density plasma and bcc-phase Tantalum (∼15μΩcm) / Tantalum Nitride (bcc-Ta/TaNx) stacked metal gate below 1.0ohm/sq. In order to avoid deteriorating the metal gate system, we adopted a low-temperature S/D annealing by Solid Phase Epitaxy (SPE) method. In this paper, we demonstrate an excellent characteristic of Fully-Depleted Silicon-On-Dielectric (FDSOI) metal gate MNSFETs having conventional plane gate structure featuring fully low-temperature processing below 450°C.

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Low resistivity bcc-Ta/TaNx metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450°C

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