Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi xO y barrier layer

T. Usui; H. Nasu; J. Koike; M. Wada; S. Takahashi; N. Shimizu; T. Nishikawa; M. Yoshimaru; H. Shibata

Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi _xO _y barrier layer

T. Usui, H. Nasu, J. Koike, M. Wada, S. Takahashi, N. Shimizu, T. Nishikawa, M. Yoshimaru, H. Shibata

ENG - Materials Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

Copper (Cu) dual damascene interconnects with self-formed MnSi _xO _y barrier layer using Cu-Manganese (Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process probably because of better adhesion strength between MnSi _xO _y barrier and dielectric. More than 90% yield is obtained for 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2nm thick and continuous MnSi _xO _y layer is formed at the interface between Cu and dielectric of the via and trench and that no barrier at the via bottom. This via structure without the bottom barrier provides essential advantages of reducing via resistance, significant via-electromigration lifetime improvement due to no flux divergence site at the via and excellent stress-induced voiding performance.

Original language	English
Title of host publication	Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC
Pages	188-190
Number of pages	3
Publication status	Published - 2005 Dec 7
Event	IEEE 2005 International Interconnect Technology Conference, IITC - Burlingame, CA, United States Duration: 2005 Jun 6 → 2005 Jun 8

Publication series

Name	Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Other

Other	IEEE 2005 International Interconnect Technology Conference, IITC
Country/Territory	United States
City	Burlingame, CA
Period	05/6/6 → 05/6/8

ASJC Scopus subject areas

Engineering(all)

Cite this

Usui, T., Nasu, H., Koike, J., Wada, M., Takahashi, S., Shimizu, N., Nishikawa, T., Yoshimaru, M., & Shibata, H. (2005). Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi _xO _y barrier layer. In Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC (pp. 188-190). [9.2] (Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC).

Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi _xO _y barrier layer. / Usui, T.; Nasu, H.; Koike, J. et al.

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC. 2005. p. 188-190 9.2 (Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usui, T, Nasu, H, Koike, J, Wada, M, Takahashi, S, Shimizu, N, Nishikawa, T, Yoshimaru, M & Shibata, H 2005, Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi _xO _y barrier layer. in Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC., 9.2, Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC, pp. 188-190, IEEE 2005 International Interconnect Technology Conference, IITC, Burlingame, CA, United States, 05/6/6.

Usui T, Nasu H, Koike J, Wada M, Takahashi S, Shimizu N et al. Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi _xO _y barrier layer. In Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC. 2005. p. 188-190. 9.2. (Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC).

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abstract = "Copper (Cu) dual damascene interconnects with self-formed MnSi xO y barrier layer using Cu-Manganese (Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process probably because of better adhesion strength between MnSi xO y barrier and dielectric. More than 90% yield is obtained for 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2nm thick and continuous MnSi xO y layer is formed at the interface between Cu and dielectric of the via and trench and that no barrier at the via bottom. This via structure without the bottom barrier provides essential advantages of reducing via resistance, significant via-electromigration lifetime improvement due to no flux divergence site at the via and excellent stress-induced voiding performance.",

author = "T. Usui and H. Nasu and J. Koike and M. Wada and S. Takahashi and N. Shimizu and T. Nishikawa and M. Yoshimaru and H. Shibata",

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note = "IEEE 2005 International Interconnect Technology Conference, IITC ; Conference date: 06-06-2005 Through 08-06-2005",

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T1 - Low resistive and highly reliable Cu dual-damascene interconnect technology using self-formed mnSi xO y barrier layer

AU - Usui, T.

AU - Nasu, H.

AU - Koike, J.

AU - Wada, M.

AU - Takahashi, S.

AU - Shimizu, N.

AU - Nishikawa, T.

AU - Yoshimaru, M.

AU - Shibata, H.

PY - 2005/12/7

Y1 - 2005/12/7

N2 - Copper (Cu) dual damascene interconnects with self-formed MnSi xO y barrier layer using Cu-Manganese (Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process probably because of better adhesion strength between MnSi xO y barrier and dielectric. More than 90% yield is obtained for 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2nm thick and continuous MnSi xO y layer is formed at the interface between Cu and dielectric of the via and trench and that no barrier at the via bottom. This via structure without the bottom barrier provides essential advantages of reducing via resistance, significant via-electromigration lifetime improvement due to no flux divergence site at the via and excellent stress-induced voiding performance.

AB - Copper (Cu) dual damascene interconnects with self-formed MnSi xO y barrier layer using Cu-Manganese (Mn) alloy seed layer is successfully fabricated for the first time. No delamination is found in the chemical mechanical polishing process probably because of better adhesion strength between MnSi xO y barrier and dielectric. More than 90% yield is obtained for 1 million via chain. Microstructure analysis by transmission electron microscopy shows that an approximately 2nm thick and continuous MnSi xO y layer is formed at the interface between Cu and dielectric of the via and trench and that no barrier at the via bottom. This via structure without the bottom barrier provides essential advantages of reducing via resistance, significant via-electromigration lifetime improvement due to no flux divergence site at the via and excellent stress-induced voiding performance.

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