Low power neuron-MOS technology for high-functionality logic gate synthesis

Ho Yup Kwon; Koji Kotani; Tadashi Shibata; Tadahiro Ohmi

Low power neuron-MOS technology for high-functionality logic gate synthesis

Ho Yup Kwon, Koji Kotani, Tadashi Shibata, Tadahiro Ohmi

ENG - Electronic Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

Original language	English
Pages (from-to)	924-929
Number of pages	6
Journal	IEICE Transactions on Electronics
Volume	E80-C
Issue number	7
Publication status	Published - 1997 Jan 1

Keywords

Deep-threshold
Full adder
Low power
Neuron MOS
Number detector

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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@article{1769f13158a44106a7477cc0e042ea07,

title = "Low power neuron-MOS technology for high-functionality logic gate synthesis",

abstract = "The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.",

keywords = "Deep-threshold, Full adder, Low power, Neuron MOS, Number detector",

author = "Kwon, {Ho Yup} and Koji Kotani and Tadashi Shibata and Tadahiro Ohmi",

year = "1997",

month = jan,

day = "1",

language = "English",

volume = "E80-C",

pages = "924--929",

journal = "IEICE Transactions on Electronics",

issn = "0916-8524",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "7",

}

TY - JOUR

T1 - Low power neuron-MOS technology for high-functionality logic gate synthesis

AU - Kwon, Ho Yup

AU - Kotani, Koji

AU - Shibata, Tadashi

AU - Ohmi, Tadahiro

PY - 1997/1/1

Y1 - 1997/1/1

N2 - The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

AB - The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

KW - Deep-threshold

KW - Full adder

KW - Low power

KW - Neuron MOS

KW - Number detector

UR - http://www.scopus.com/inward/record.url?scp=0031190331&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031190331&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0031190331

VL - E80-C

SP - 924

EP - 929

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 7

ER -

Low power neuron-MOS technology for high-functionality logic gate synthesis

Abstract

Keywords

ASJC Scopus subject areas

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