Abstract
The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.
Original language | English |
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Pages (from-to) | 924-929 |
Number of pages | 6 |
Journal | IEICE Transactions on Electronics |
Volume | E80-C |
Issue number | 7 |
Publication status | Published - 1997 Jan 1 |
Keywords
- Deep-threshold
- Full adder
- Low power
- Neuron MOS
- Number detector
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering