Low-power multiple-valued source-coupled logic circuits using dual-supply voltages for a reconfigurable VLSI

Xu Bai; Michitaka Kameyama

doi:10.1109/ISMVL.2013.36

Low-power multiple-valued source-coupled logic circuits using dual-supply voltages for a reconfigurable VLSI

Xu Bai, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-VDD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.

Original language	English
Title of host publication	Proceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
Pages	164-169
Number of pages	6
DOIs	https://doi.org/10.1109/ISMVL.2013.36
Publication status	Published - 2013 Aug 1
Event	2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013 - Toyama, Japan Duration: 2013 May 22 → 2013 May 24

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
Country	Japan
City	Toyama
Period	13/5/22 → 13/5/24

Keywords

Dual-supply-voltage technique
Multiple-valued reconfigurable VLSI
Multiple-valued source-coupled logic circuit

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Access to Document

10.1109/ISMVL.2013.36

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Low-power multiple-valued source-coupled logic circuits using dual-supply voltages for a reconfigurable VLSI. / Bai, Xu; Kameyama, Michitaka.

Proceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013. 2013. p. 164-169 6524657 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bai, X & Kameyama, M 2013, Low-power multiple-valued source-coupled logic circuits using dual-supply voltages for a reconfigurable VLSI. in Proceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013., 6524657, Proceedings of The International Symposium on Multiple-Valued Logic, pp. 164-169, 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013, Toyama, Japan, 13/5/22. https://doi.org/10.1109/ISMVL.2013.36

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abstract = "A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-VDD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.",

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N2 - A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-VDD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.

AB - A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-VDD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.

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Low-power multiple-valued source-coupled logic circuits using dual-supply voltages for a reconfigurable VLSI

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