TY - GEN
T1 - Low-power multiple-valued source-coupled logic circuits using dual-supply voltages for a reconfigurable VLSI
AU - Bai, Xu
AU - Kameyama, Michitaka
PY - 2013/8/1
Y1 - 2013/8/1
N2 - A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-VDD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.
AB - A novel dual-supply-voltage technique is proposed for a low-power multiple-valued VLSI without decreasing speed. A high-supply voltage is required to generate multiple-valued voltage signals in a current-voltage converter, and a low-supply voltage is used to generate binary voltage signals in a comparator whose speed is not decreased by the low-supply voltage. Moreover, level shifters used to prevent direct-path currents in the conventional dual-VDD CMOS circuits are not necessary to be provided because of constant current flow in the multiple-valued source-coupled logic circuits. As a result, the power consumption of a cell using dual-supply voltages for a multiple-valued reconfigurable VLSI is reduced to 79% in comparison with that of the cell using a single-supply voltage.
KW - Dual-supply-voltage technique
KW - Multiple-valued reconfigurable VLSI
KW - Multiple-valued source-coupled logic circuit
UR - http://www.scopus.com/inward/record.url?scp=84880706371&partnerID=8YFLogxK
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U2 - 10.1109/ISMVL.2013.36
DO - 10.1109/ISMVL.2013.36
M3 - Conference contribution
AN - SCOPUS:84880706371
SN - 9780769549767
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 164
EP - 169
BT - Proceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
T2 - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
Y2 - 22 May 2013 through 24 May 2013
ER -