Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

Nobuaki Okada, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

Original languageEnglish
Pages (from-to)619-631
Number of pages13
JournalJournal of Multiple-Valued Logic and Soft Computing
Volume13
Issue number4-6
Publication statusPublished - 2007 Nov 29

Keywords

  • Direct allocation of control/data flow graph
  • Fine-grain reconfigurable VLSI
  • Low-power VLSI design
  • Multiple-valued VLSI
  • Multiple-valued source-coupled logic
  • Universal literal

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

Fingerprint Dive into the research topics of 'Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits'. Together they form a unique fingerprint.

Cite this