Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

Nobuaki Okada; Michitaka Kameyama

doi:10.1109/ISMVL.2007.32

Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

Nobuaki Okada, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

Original language	English
Title of host publication	37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOIs	https://doi.org/10.1109/ISMVL.2007.32
Publication status	Published - 2007 Sep 3
Event	37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway Duration: 2007 May 13 → 2007 May 16

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

Other

Other	37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Country/Territory	Norway
City	Oslo
Period	07/5/13 → 07/5/16

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Access to Document

10.1109/ISMVL.2007.32

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Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits. / Okada, Nobuaki; Kameyama, Michitaka.

37th International Symposium on Multiple-Valued Logic, ISMVL 2007. 2007. 4215948 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okada, N & Kameyama, M 2007, Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits. in 37th International Symposium on Multiple-Valued Logic, ISMVL 2007., 4215948, Proceedings of The International Symposium on Multiple-Valued Logic, 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, Oslo, Norway, 07/5/13. https://doi.org/10.1109/ISMVL.2007.32

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AB - A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

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Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

Abstract

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