Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits

Nobuaki Okada, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.

Original languageEnglish
Title of host publication37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOIs
Publication statusPublished - 2007 Sep 3
Event37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway
Duration: 2007 May 132007 May 16

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other37th International Symposium on Multiple-Valued Logic, ISMVL 2007
CountryNorway
CityOslo
Period07/5/1307/5/16

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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    Okada, N., & Kameyama, M. (2007). Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits. In 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 [4215948] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2007.32