TY - GEN
T1 - Low-power multiple-valued reconfigurable VLSI using series-gating differential-pair circuits
AU - Okada, Nobuaki
AU - Kameyama, Michitaka
PY - 2007/9/3
Y1 - 2007/9/3
N2 - A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.
AB - A new cell for multiple-valued reconfigurable VLSI based on source-coupled logic is proposed to implement low-power high-performance random logic network. The cell has a function of a 4-valued universal literal which can be implemented using a Series-Gating Differential-Pair Circuit (SGDPC) having only one current source. A 4-valued universal literal can be realized by programming two subfunctions called half-universal literals. To reduce power consumption of a standby cell, ON/OFF-control and leakage-current reduction schemes are introduced in the current source. These technologies are effectively employed for low-power reconfigurable VLSI computing.
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U2 - 10.1109/ISMVL.2007.32
DO - 10.1109/ISMVL.2007.32
M3 - Conference contribution
AN - SCOPUS:34548201692
SN - 0769528317
SN - 9780769528311
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
BT - 37th International Symposium on Multiple-Valued Logic, ISMVL 2007
T2 - 37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Y2 - 13 May 2007 through 16 May 2007
ER -