TY - GEN
T1 - Low-power multiple-valued reconfigurable VLSI based on superposition of bit-serial data and current-source control signals
AU - Ishikawa, Akitaka
AU - Okada, Nobuaki
AU - Kameyama, Michitaka
PY - 2010/8/12
Y1 - 2010/8/12
N2 - A bit-serial multiple-valued reconfigurable VLSI using current-mode logic circuits has been proposed. A Differential-Pair Circuit (DPC) is used as a basic component of a cell, so that the static power is dissipated even in the nonactive cells. To solve the problem, autonomous ON/OFF control of the current sources is presented based on superposition of bit-serial data and current-source control signals. In the proposed switched current control technique, the static power dissipation can be greatly reduced because current sources in nonactive circuit blocks are turned off. The superposition of data and control signals in a single interconnection is effectively utilized to reduce complexity of switches and interconnections, and to eliminate skew between data and control signals. It is evaluated that the reduction of the power dissipation is remarkable, if the operating ratio is less than 75%.
AB - A bit-serial multiple-valued reconfigurable VLSI using current-mode logic circuits has been proposed. A Differential-Pair Circuit (DPC) is used as a basic component of a cell, so that the static power is dissipated even in the nonactive cells. To solve the problem, autonomous ON/OFF control of the current sources is presented based on superposition of bit-serial data and current-source control signals. In the proposed switched current control technique, the static power dissipation can be greatly reduced because current sources in nonactive circuit blocks are turned off. The superposition of data and control signals in a single interconnection is effectively utilized to reduce complexity of switches and interconnections, and to eliminate skew between data and control signals. It is evaluated that the reduction of the power dissipation is remarkable, if the operating ratio is less than 75%.
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U2 - 10.1109/ISMVL.2010.41
DO - 10.1109/ISMVL.2010.41
M3 - Conference contribution
AN - SCOPUS:77955328808
SN - 9780769540245
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 179
EP - 184
BT - ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic
T2 - 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010
Y2 - 26 May 2010 through 28 May 2010
ER -