Abstract
A new circuit technique based on pass-gate logic with dynamic supply-voltage and clock-frequency control is proposed for a low-power motion-vector detection VLSI processor. Since the pass-gate logic style has potential advantages that have small equivalent stray capacitance and small number of short-circuit paths, its circuit implementation makes it possible to reduce the power dissipation with maintaining high-speed switching capability. In case the calculation result is obtained on the way of calculation steps, additional power saving is also achieved by combining the pass-gate logic circuitry with a mechanism that dynamically scales down the supply voltage and the clock frequency while maintaining the calculation throughput. As a typical example, a sum of absolute differences (SAD) unit in a motion-vector detection VLSI processor is implemented and its efficiency in power saving is demonstrated.
Original language | English |
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Pages (from-to) | 1876-1883 |
Number of pages | 8 |
Journal | IEICE Transactions on Electronics |
Volume | E87-C |
Issue number | 11 |
Publication status | Published - 2004 Nov |
Externally published | Yes |
Keywords
- Clock-frequency control
- Cmos pass gate
- Motion-vector detection
- Sum of absolute differences
- Supply-voltage control
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering