Low-power field-programmable VLSI processor using dynamic circuits

Weisheng Chong, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper proposes a low-power field-programmable VLSI processor (FPVLSI) to overcome the problem of large power consumption infield-programmable gate arrays (FPGAs). A bit-serial pipeline architecture is used in the FPVLSI to reduce the complexity of interconnection blocks. Moreover, a dual-supply-voltage scheme is effectively used to scale down the supply voltage along non-critical paths to obtain low power consumption without degrading the over-all speed performance. Its main drawback is the additional hardware cost of level converters to connect a low-supply-voltage module with a high-supply-voltage one. To solve this problem, a level-converter-less look-up table based on dynamic circuits is presented. The dynamic circuits are also useful to reduce glitch power that is one of the significant portions of the total power in FPGAs. The FPVLSI is designed based on a 0.18-μm CMOS design rule. The power consumption of the FPVLSI is reduced to 40% compared to that of the FPGA.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging Trends in VLSI Systems Design
EditorsA. Smailagic, M. Bayoumi
Pages243-248
Number of pages6
Publication statusPublished - 2004 Sep 24
EventProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States
Duration: 2004 Feb 192004 Feb 20

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

OtherProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
CountryUnited States
CityLafayette, LA
Period04/2/1904/2/20

ASJC Scopus subject areas

  • Engineering(all)

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