Low power consumption and fast settling frequency synthesizer for TDMA-TDD systems

Kazuhiko Seki, Masato Mizoguchi, Shuuzou Kato

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposed a novel configuration for a low power consumption, fast settling frequency synthesizer. The synthesizer employs two sets of a sample-hold VCO and a carrier switch which selects VCO output as the output of the synthesizer burst-by-burst.The frequency settling time of the synthesizer is drastically reduced below a few nano seconds which is much shorter than the guard time duration of the TDMA-TDD frame. The power consumption is less than 65% of that of the conventional synthesizer with dual PLL circuits. The frequency error caused by the sample-hold circuit is analyzed theoretically and experimentally. The results confirm that the theoretical analyses give a good approximation and show that the longer acquisition time of the sample-hold circuit minimizes the frequency error at the synthesizer output.

Original languageEnglish
Title of host publicationIEEE Vehicular Technology Conference
PublisherPubl by IEEE
Pages281-284
Number of pages4
ISBN (Print)078031266X
Publication statusPublished - 1993 Jan 1
EventProceedings of the 43rd IEEE Vehicular Technology Conference - Secaucus, NJ, USA
Duration: 1993 May 181993 May 20

Publication series

NameIEEE Vehicular Technology Conference
ISSN (Print)0740-0551

Other

OtherProceedings of the 43rd IEEE Vehicular Technology Conference
CitySecaucus, NJ, USA
Period93/5/1893/5/20

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Applied Mathematics

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  • Cite this

    Seki, K., Mizoguchi, M., & Kato, S. (1993). Low power consumption and fast settling frequency synthesizer for TDMA-TDD systems. In IEEE Vehicular Technology Conference (pp. 281-284). (IEEE Vehicular Technology Conference). Publ by IEEE.