Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay

T. Hoffmann; A. Veloso; A. Lauwers; H. Yu; M. Van Dal; H. Tigelaar; T. Chiarella; C. Kerner; R. Mitsuhashi; I. Satoru; M. Niwa; A. Rothschild; B. Froment; J. Ramos; A. Nackaerts; S. Brus; C. Vrancken; P. P. Absil; M. Jurczak; J. A. Kittl; S. Biesemans

Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay

T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, M. Van Dal, H. Tigelaar, T. Chiarella, C. Kerner, R. Mitsuhashi, I. Satoru, M. Niwa, A. Rothschild, B. Froment, J. Ramos, A. Nackaerts, S. Brus, C. Vrancken, P. P. Absil, M. Jurczak, J. A. KittlS. Biesemans

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

We report record unloaded ring oscillator delay (17ps at V _DD=1.1V and 20pA/μm I_off) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report [1]. First, we have improved the (unstrained) devices Idsat to be 560/245μA/μm for nMOS/pMOS at an I_off=20pA/μm and V_DD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lg_min reduction of 7nm/14nm for nMOS/pMOS over our Poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional Poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN).

Original language	English
Title of host publication	2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
Pages	154-155
Number of pages	2
Publication status	Published - 2006
Externally published	Yes
Event	2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States Duration: 2006 Jun 13 → 2006 Jun 15

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2006 Symposium on VLSI Technology, VLSIT
Country/Territory	United States
City	Honolulu, HI
Period	06/6/13 → 06/6/15

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Hoffmann, T., Veloso, A., Lauwers, A., Yu, H., Van Dal, M., Tigelaar, H., Chiarella, T., Kerner, C., Mitsuhashi, R., Satoru, I., Niwa, M., Rothschild, A., Froment, B., Ramos, J., Nackaerts, A., Brus, S., Vrancken, C., Absil, P. P., Jurczak, M., ... Biesemans, S. (2006). Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay. In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers (pp. 154-155). [1705263] (Digest of Technical Papers - Symposium on VLSI Technology).

Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay. / Hoffmann, T.; Veloso, A.; Lauwers, A. et al.

2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. 2006. p. 154-155 1705263 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hoffmann, T, Veloso, A, Lauwers, A, Yu, H, Van Dal, M, Tigelaar, H, Chiarella, T, Kerner, C, Mitsuhashi, R, Satoru, I, Niwa, M, Rothschild, A, Froment, B, Ramos, J, Nackaerts, A, Brus, S, Vrancken, C, Absil, PP, Jurczak, M, Kittl, JA & Biesemans, S 2006, Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay. in 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers., 1705263, Digest of Technical Papers - Symposium on VLSI Technology, pp. 154-155, 2006 Symposium on VLSI Technology, VLSIT, Honolulu, HI, United States, 06/6/13.

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title = "Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay",

abstract = "We report record unloaded ring oscillator delay (17ps at V DD=1.1V and 20pA/μm Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report [1]. First, we have improved the (unstrained) devices Idsat to be 560/245μA/μm for nMOS/pMOS at an Ioff=20pA/μm and VDD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lgmin reduction of 7nm/14nm for nMOS/pMOS over our Poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional Poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN).",

author = "T. Hoffmann and A. Veloso and A. Lauwers and H. Yu and {Van Dal}, M. and H. Tigelaar and T. Chiarella and C. Kerner and R. Mitsuhashi and I. Satoru and M. Niwa and A. Rothschild and B. Froment and J. Ramos and A. Nackaerts and S. Brus and C. Vrancken and Absil, {P. P.} and M. Jurczak and Kittl, {J. A.} and S. Biesemans",

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series = "Digest of Technical Papers - Symposium on VLSI Technology",

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note = "2006 Symposium on VLSI Technology, VLSIT ; Conference date: 13-06-2006 Through 15-06-2006",

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T1 - Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay

AU - Hoffmann, T.

AU - Veloso, A.

AU - Lauwers, A.

AU - Yu, H.

AU - Van Dal, M.

AU - Tigelaar, H.

AU - Chiarella, T.

AU - Kerner, C.

AU - Mitsuhashi, R.

AU - Satoru, I.

AU - Niwa, M.

AU - Rothschild, A.

AU - Froment, B.

AU - Ramos, J.

AU - Nackaerts, A.

AU - Brus, S.

AU - Vrancken, C.

AU - Absil, P. P.

AU - Jurczak, M.

AU - Kittl, J. A.

AU - Biesemans, S.

PY - 2006

Y1 - 2006

N2 - We report record unloaded ring oscillator delay (17ps at V DD=1.1V and 20pA/μm Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report [1]. First, we have improved the (unstrained) devices Idsat to be 560/245μA/μm for nMOS/pMOS at an Ioff=20pA/μm and VDD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lgmin reduction of 7nm/14nm for nMOS/pMOS over our Poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional Poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN).

AB - We report record unloaded ring oscillator delay (17ps at V DD=1.1V and 20pA/μm Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report [1]. First, we have improved the (unstrained) devices Idsat to be 560/245μA/μm for nMOS/pMOS at an Ioff=20pA/μm and VDD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lgmin reduction of 7nm/14nm for nMOS/pMOS over our Poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional Poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN).

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AN - SCOPUS:41149119018

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T3 - Digest of Technical Papers - Symposium on VLSI Technology

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EP - 155

BT - 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers

T2 - 2006 Symposium on VLSI Technology, VLSIT

Y2 - 13 June 2006 through 15 June 2006

ER -

Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay

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