Low power CMOS featuring dual work function FUSI on HfSiON and 17ps inverter delay

T. Hoffmann, A. Veloso, A. Lauwers, H. Yu, M. Van Dal, H. Tigelaar, T. Chiarella, C. Kerner, R. Mitsuhashi, I. Satoru, M. Niwa, A. Rothschild, B. Froment, J. Ramos, A. Nackaerts, S. Brus, C. Vrancken, P. P. Absil, M. Jurczak, J. A. KittlS. Biesemans

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We report record unloaded ring oscillator delay (17ps at V DD=1.1V and 20pA/μm Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report [1]. First, we have improved the (unstrained) devices Idsat to be 560/245μA/μm for nMOS/pMOS at an Ioff=20pA/μm and VDD=1.1V. Second, we demonstrate that the use of metal gates enables a reduction of the junction anneal temperature, yielding an Lgmin reduction of 7nm/14nm for nMOS/pMOS over our Poly-Si/SiON reference. We also report for the first time that metal gate on HfSiON devices can outperform optimized conventional Poly-Si/SiON devices by up to 25% in unloaded ring oscillator speed. Finally, our study shows that there is no intrinsic difference between Ni-FUSI compared to inserted metal gates (TiN, TaN).

Original languageEnglish
Title of host publication2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
Pages154-155
Number of pages2
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States
Duration: 2006 Jun 132006 Jun 15

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2006 Symposium on VLSI Technology, VLSIT
Country/TerritoryUnited States
CityHonolulu, HI
Period06/6/1306/6/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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