Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks

Naoya Onizawa, Warren J. Gross

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We propose a novel architecture for low-power area-efficient large-scale IP lookup engines. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry search of input addresses in TCAMs. The proposed hardware that stores 100,000 144-bit entries is evaluated under TSMC 65nm CMOS technology. The dynamic power dissipation and the area of the proposed hardware are 4.6% and 30.6% of a traditional TCAM, respectively while maintaining comparable throughput.

Original languageEnglish
Title of host publicationProceedings of the 50th Annual Design Automation Conference, DAC 2013
DOIs
Publication statusPublished - 2013 Jul 12
Externally publishedYes
Event50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
Duration: 2013 May 292013 Jun 7

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference50th Annual Design Automation Conference, DAC 2013
CountryUnited States
CityAustin, TX
Period13/5/2913/6/7

Keywords

  • Associative memory
  • Neural network
  • TCAM

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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  • Cite this

    Onizawa, N., & Gross, W. J. (2013). Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. In Proceedings of the 50th Annual Design Automation Conference, DAC 2013 [55] (Proceedings - Design Automation Conference). https://doi.org/10.1145/2463209.2488801