Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices

Y. Matsubara; K. Endo; T. Tatsumi; H. Ueno; K. Sugai; T. Horiuchi

Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices

Y. Matsubara, K. Endo, T. Tatsumi, H. Ueno, K. Sugai, T. Horiuchi

Research output: Contribution to journal › Conference article › peer-review

Abstract

We have developed a new interlayer technology that attain 50% reduction in capacitance and keep good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) process. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO₂, which are formed in sequential by high density plasma-chemical vapor deposition (HDP-CVD) technique. Top SiO₂ layer assures oxygen plasma resistance during via etching, metal etching, and resist removal.

Original language	English
Pages (from-to)	369-372
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1996 Dec 1
Externally published	Yes
Event	Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 1996 Dec 8 → 1996 Dec 11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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title = "Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices",

abstract = "We have developed a new interlayer technology that attain 50% reduction in capacitance and keep good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) process. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO2, which are formed in sequential by high density plasma-chemical vapor deposition (HDP-CVD) technique. Top SiO2 layer assures oxygen plasma resistance during via etching, metal etching, and resist removal.",

author = "Y. Matsubara and K. Endo and T. Tatsumi and H. Ueno and K. Sugai and T. Horiuchi",

year = "1996",

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language = "English",

pages = "369--372",

journal = "Technical Digest - International Electron Devices Meeting",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1996 IEEE International Electron Devices Meeting ; Conference date: 08-12-1996 Through 11-12-1996",

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T1 - Low-k fluorinated amorphous carbon interlayer technology for quarter micron devices

AU - Matsubara, Y.

AU - Endo, K.

AU - Tatsumi, T.

AU - Ueno, H.

AU - Sugai, K.

AU - Horiuchi, T.

PY - 1996/12/1

Y1 - 1996/12/1

N2 - We have developed a new interlayer technology that attain 50% reduction in capacitance and keep good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) process. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO2, which are formed in sequential by high density plasma-chemical vapor deposition (HDP-CVD) technique. Top SiO2 layer assures oxygen plasma resistance during via etching, metal etching, and resist removal.

AB - We have developed a new interlayer technology that attain 50% reduction in capacitance and keep good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) process. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO2, which are formed in sequential by high density plasma-chemical vapor deposition (HDP-CVD) technique. Top SiO2 layer assures oxygen plasma resistance during via etching, metal etching, and resist removal.

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M3 - Conference article

AN - SCOPUS:0030409311

SP - 369

EP - 372

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - Proceedings of the 1996 IEEE International Electron Devices Meeting

Y2 - 8 December 1996 through 11 December 1996

ER -