Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60nm CMOS technology on 300mm wafer process

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f ) noise. The measurement results show that the fabricated V-MOSFETs with 60nm silicon pillar and 100nm gate length achieve excellent steep sub-threshold swing (69mV/decade for n-type and 66mV/decade for p-type), good on-current (281 μA/μm for n-type 149 μA/μm for p-type), low off-leakage current (28.1 pA/μm for n-type and 79.6 pA/μm for p-type), and excellent on-off ratio (1 × 10⁷ for n-type and 2 × 10⁶ for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (V_th) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control V_th more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L_gateWS_Id=I²_d of 10^-13-10^-11μm²/Hz for n-type and 10^-12-10^-10μm²/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.