TY - JOUR
T1 - Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60nm CMOS technology on 300mm wafer process
AU - Imamoto, Takuya
AU - Ma, Yitao
AU - Muraguchi, Masakazu
AU - Endoh, Tetsuo
N1 - Publisher Copyright:
© 2015 The Japan Society of Applied Physics.
PY - 2015/4/1
Y1 - 2015/4/1
N2 - In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f ) noise. The measurement results show that the fabricated V-MOSFETs with 60nm silicon pillar and 100nm gate length achieve excellent steep sub-threshold swing (69mV/decade for n-type and 66mV/decade for p-type), good on-current (281 μA/μm for n-type 149 μA/μm for p-type), low off-leakage current (28.1 pA/μm for n-type and 79.6 pA/μm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (LgateWSId=I2d of 10-13-10-11μm2/Hz for n-type and 10-12-10-10μm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.
AB - In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f ) noise. The measurement results show that the fabricated V-MOSFETs with 60nm silicon pillar and 100nm gate length achieve excellent steep sub-threshold swing (69mV/decade for n-type and 66mV/decade for p-type), good on-current (281 μA/μm for n-type 149 μA/μm for p-type), low off-leakage current (28.1 pA/μm for n-type and 79.6 pA/μm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (LgateWSId=I2d of 10-13-10-11μm2/Hz for n-type and 10-12-10-10μm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.
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U2 - 10.7567/JJAP.54.04DC11
DO - 10.7567/JJAP.54.04DC11
M3 - Article
AN - SCOPUS:84926295376
VL - 54
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 4
M1 - 04DC11
ER -