Low-energy asynchronous interleaver for clockless fully parallel LDPC decoding

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

Abstract

This paper presents a low-energy asynchronous interleaver for clockless fully parallel low-density parity-check (LDPC) decoding. The proposed data-transmission circuit based on a half-duplex single-track protocol makes it possible to realize a wire-efficient asynchronous interleaver with small energy consumption. Moreover, a data-monitoring system adaptively shuts down the asynchronous data-transmission circuit if not necessary, which reduces the number of data transmissions and, hence, the energy consumed. The clockless decoder with the proposed asynchronous interleaver is evaluated using a (1056,528) irregular LDPC code under a 90-nm CMOS process. As a result, the energy dissipation per uncoded bit at Eb/No of 5 dB becomes 54 pJ/bit with an uncoded throughput of 45.5 Gbps under a postlayout simulation. This represents a 92% decrease in energy per bit and a 1143% in throughput increase with respect to our previous clockless LDPC decoder.

Original languageEnglish
Article number5712175
Pages (from-to)1933-1943
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume58
Issue number8
DOIs
Publication statusPublished - 2011

Keywords

  • Asynchronous circuits
  • forward error control (FEC)
  • iterative decoding
  • low-density parity-check (LDPC) codes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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