Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture

Ken Nakamura; Yuya Omori; Daisuke Kobayashi; Tatsuya Osawa; Takayuki Onishi; Koyo Nitta; Hiroe Iwasaki; Atsushi Shimizu

doi:10.1109/CoolChips.2019.8721335

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture

Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper describes a novel low delay 4K 120fps real-time HEVC decoder we have developed with parallel processing architecture that conforms to the HEVC Main 4:2:2 10 profile. It supports the temporal scalable streams required for 4K high frame rate broadcasting and also supports low delay and high bitrate decoding for video transmission. To achieve this support, the decoding processes are parallelized and pipelined at frame level, slice level and Coding Tree Unit row level. The proposed decoder is implemented on three Arria10 series FPGAs operating at 133 and 150MHz, and achieves 300Mbps stream decoding and 37msec end-to-end delay with our concurrently developed 4K 120fps encoder.

Original language	English
Title of host publication	IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728117485
DOIs	https://doi.org/10.1109/CoolChips.2019.8721335
Publication status	Published - 2019 May 23
Externally published	Yes
Event	22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Yokohama, Japan Duration: 2019 Apr 17 → 2019 Apr 19

Publication series

Name	IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

Conference

Conference	22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019
Country/Territory	Japan
City	Yokohama
Period	19/4/17 → 19/4/19

Keywords

4K
Decoder
HEVC
High frame rate
Temporal scalability

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/CoolChips.2019.8721335

Cite this

Nakamura, K., Omori, Y., Kobayashi, D., Osawa, T., Onishi, T., Nitta, K., Iwasaki, H., & Shimizu, A. (2019). Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. In IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings [8721335] (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CoolChips.2019.8721335

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. / Nakamura, Ken; Omori, Yuya; Kobayashi, Daisuke et al.

IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8721335 (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nakamura, K, Omori, Y, Kobayashi, D, Osawa, T, Onishi, T, Nitta, K, Iwasaki, H & Shimizu, A 2019, Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. in IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings., 8721335, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019, Yokohama, Japan, 19/4/17. https://doi.org/10.1109/CoolChips.2019.8721335

Nakamura K, Omori Y, Kobayashi D, Osawa T, Onishi T, Nitta K et al. Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. In IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8721335. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings). doi: 10.1109/CoolChips.2019.8721335

Nakamura, Ken ; Omori, Yuya ; Kobayashi, Daisuke et al. / Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings).

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title = "Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture",

abstract = "This paper describes a novel low delay 4K 120fps real-time HEVC decoder we have developed with parallel processing architecture that conforms to the HEVC Main 4:2:2 10 profile. It supports the temporal scalable streams required for 4K high frame rate broadcasting and also supports low delay and high bitrate decoding for video transmission. To achieve this support, the decoding processes are parallelized and pipelined at frame level, slice level and Coding Tree Unit row level. The proposed decoder is implemented on three Arria10 series FPGAs operating at 133 and 150MHz, and achieves 300Mbps stream decoding and 37msec end-to-end delay with our concurrently developed 4K 120fps encoder.",

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AU - Nitta, Koyo

AU - Iwasaki, Hiroe

AU - Shimizu, Atsushi

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AB - This paper describes a novel low delay 4K 120fps real-time HEVC decoder we have developed with parallel processing architecture that conforms to the HEVC Main 4:2:2 10 profile. It supports the temporal scalable streams required for 4K high frame rate broadcasting and also supports low delay and high bitrate decoding for video transmission. To achieve this support, the decoding processes are parallelized and pipelined at frame level, slice level and Coding Tree Unit row level. The proposed decoder is implemented on three Arria10 series FPGAs operating at 133 and 150MHz, and achieves 300Mbps stream decoding and 37msec end-to-end delay with our concurrently developed 4K 120fps encoder.

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Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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