Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture

Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper describes a novel low delay 4K 120fps real-time HEVC decoder we have developed with parallel processing architecture that conforms to the HEVC Main 4:2:2 10 profile. It supports the temporal scalable streams required for 4K high frame rate broadcasting and also supports low delay and high bitrate decoding for video transmission. To achieve this support, the decoding processes are parallelized and pipelined at frame level, slice level and Coding Tree Unit row level. The proposed decoder is implemented on three Arria10 series FPGAs operating at 133 and 150MHz, and achieves 300Mbps stream decoding and 37msec end-to-end delay with our concurrently developed 4K 120fps encoder.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728117485
DOIs
Publication statusPublished - 2019 May 23
Externally publishedYes
Event22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Yokohama, Japan
Duration: 2019 Apr 172019 Apr 19

Publication series

NameIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

Conference

Conference22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019
Country/TerritoryJapan
CityYokohama
Period19/4/1719/4/19

Keywords

  • 4K
  • Decoder
  • HEVC
  • High frame rate
  • Temporal scalability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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