TY - JOUR
T1 - Loss analysis and optimum design of a highly efficient and compact CMOS DC-DC converter with novel transistor layout using 60nm multipillar-type vertical body channel MOSFET
AU - Itoh, Kazuki
AU - Endoh, Tetsuo
N1 - Funding Information:
This work has been supported by a grant from “Three-Dimensional Integrated Circuits Technology Based on Vertical BC-MOSFET and Its Advanced Application Exploration” (Research Director: Professor Tetsuo Endoh, Program Manager: Toru Masaoka) of “Accelerated Innovation Research Initiative Turning Top Science and Ideas into High-Impact Values (ACCEL)” under the Japan Science and Technology Agency (JST) Grant Number JPMJAC1301, the program on Open Innovation Platform with Enterprises, Research Institute and Academia (OPERA) from JST, and VLSI Design and Education Center (VDEC), The University of Tokyo in collaboration with Synopsys Corporation.
Publisher Copyright:
© 2018 The Japan Society of Applied Physics.
PY - 2018/4
Y1 - 2018/4
N2 - In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC-DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC-DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.
AB - In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC-DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC-DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.
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U2 - 10.7567/JJAP.57.04FR12
DO - 10.7567/JJAP.57.04FR12
M3 - Article
AN - SCOPUS:85044472235
VL - 57
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 4
M1 - 04FR12
ER -