Loss analysis and optimum design of a highly efficient and compact CMOS DC-DC converter with novel transistor layout using 60nm multipillar-type vertical body channel MOSFET

Kazuki Itoh, Tetsuo Endoh

Research output: Contribution to journalArticle

Abstract

In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC-DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC-DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.

Original languageEnglish
Article number04FR12
JournalJapanese journal of applied physics
Volume57
Issue number4
DOIs
Publication statusPublished - 2018 Apr

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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