Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

Y. X. Liu; T. Sekigawa; T. Hayashida; T. Matsukawa; K. Endo; S. O'Uchi; K. Sakamoto; K. Ishii; T. Tsukada; Y. Ishikawa; H. Yamauchi; A. Ogura; H. Koike; E. Suzuki; M. Masahara

doi:10.1109/SOI.2008.4656344

Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

Y. X. Liu, T. Sekigawa, T. Hayashida, T. Matsukawa, K. Endo, S. O'Uchi, K. Sakamoto, K. Ishii, T. Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, H. Koike, E. Suzuki, M. Masahara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Original language	English
Title of host publication	2008 IEEE International SOI Conference Proceedings
Pages	161-162
Number of pages	2
DOIs	https://doi.org/10.1109/SOI.2008.4656344
Publication status	Published - 2008 Dec 24
Externally published	Yes
Event	2008 IEEE International SOI Conference - New Paltz, NY, United States Duration: 2008 Oct 6 → 2008 Oct 9

Publication series

Name	Proceedings - IEEE International SOI Conference
ISSN (Print)	1078-621X

Other

Other	2008 IEEE International SOI Conference
Country/Territory	United States
City	New Paltz, NY
Period	08/10/6 → 08/10/9

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/SOI.2008.4656344

Cite this

Liu, Y. X., Sekigawa, T., Hayashida, T., Matsukawa, T., Endo, K., O'Uchi, S., Sakamoto, K., Ishii, K., Tsukada, T., Ishikawa, Y., Yamauchi, H., Ogura, A., Koike, H., Suzuki, E., & Masahara, M. (2008). Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. In 2008 IEEE International SOI Conference Proceedings (pp. 161-162). [4656344] (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2008.4656344

Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. / Liu, Y. X.; Sekigawa, T.; Hayashida, T.; Matsukawa, T.; Endo, K.; O'Uchi, S.; Sakamoto, K.; Ishii, K.; Tsukada, T.; Ishikawa, Y.; Yamauchi, H.; Ogura, A.; Koike, H.; Suzuki, E.; Masahara, M.

2008 IEEE International SOI Conference Proceedings. 2008. p. 161-162 4656344 (Proceedings - IEEE International SOI Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Liu, YX, Sekigawa, T, Hayashida, T, Matsukawa, T, Endo, K, O'Uchi, S, Sakamoto, K, Ishii, K, Tsukada, T, Ishikawa, Y, Yamauchi, H, Ogura, A, Koike, H, Suzuki, E & Masahara, M 2008, Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. in 2008 IEEE International SOI Conference Proceedings., 4656344, Proceedings - IEEE International SOI Conference, pp. 161-162, 2008 IEEE International SOI Conference, New Paltz, NY, United States, 08/10/6. https://doi.org/10.1109/SOI.2008.4656344

Liu YX, Sekigawa T, Hayashida T, Matsukawa T, Endo K, O'Uchi S et al. Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. In 2008 IEEE International SOI Conference Proceedings. 2008. p. 161-162. 4656344. (Proceedings - IEEE International SOI Conference). https://doi.org/10.1109/SOI.2008.4656344

Liu, Y. X. ; Sekigawa, T. ; Hayashida, T. ; Matsukawa, T. ; Endo, K. ; O'Uchi, S. ; Sakamoto, K. ; Ishii, K. ; Tsukada, T. ; Ishikawa, Y. ; Yamauchi, H. ; Ogura, A. ; Koike, H. ; Suzuki, E. ; Masahara, M. / Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs. 2008 IEEE International SOI Conference Proceedings. 2008. pp. 161-162 (Proceedings - IEEE International SOI Conference).

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title = "Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs",

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AU - Matsukawa, T.

AU - Endo, K.

AU - O'Uchi, S.

AU - Sakamoto, K.

AU - Ishii, K.

AU - Tsukada, T.

AU - Ishikawa, Y.

AU - Yamauchi, H.

AU - Ogura, A.

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AU - Suzuki, E.

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Logic gate threshold voltage controllable single metal gate FinFET CMOS inverters implemented by using co-integration of 3T/4T-FinFETs

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