The clear periodic thermal deformation and thus, the periodic thermal residual stress distribution appears in each chip in three-dimensionally stacked chip structures due to the periodic alignment of metallic small bumps when the thickness of a chip is decreased to less than 200 μm. The estimated local deformation was validated by using a scanning blue laser microscope. It reached about 180 nm when the thickness of the stacked chip was 100 μm. The local distribution of the residual thermal stress was also measured by using stress-sensing test chips which consisted of about 1400 2-μm-long strain gauges. It was found that the residual stress varied from -200 MPa to +100 MPa depending on the position of the chip in the stacked structure and the layout of the small bumps. Finally electronic function shift of transistors formed near the strain gauges were measured between two bumps. For example, the amplitude of a periodic distribution of the function change of 90-nm-gate NMOS transistors between two bumps reached about 8%. Therefore, it is very important to minimize the local thermal deformation and residual stress of three-dimensionally stacked chips to assure the reliable electronic performance of products.