LIMIT CYCLE-FREE 2-D SEPARABLE DENOMINATOR DIGITAL FILTERS UNDER ANY CONSTANT INPUT CONDITIONS.

Masayuki Kawamata; Tatsuo Higuchi

LIMIT CYCLE-FREE 2-D SEPARABLE DENOMINATOR DIGITAL FILTERS UNDER ANY CONSTANT INPUT CONDITIONS.

Masayuki Kawamata, Tatsuo Higuchi

ENG - Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero input limit cycles.

Original language	English
Pages (from-to)	373-375
Number of pages	3
Journal	Transactions of the Institute of Electronics, Information and Communication Engineers, Section E (
Volume	E70
Issue number	4
Publication status	Published - 1987 Apr 1

ASJC Scopus subject areas

Engineering(all)

Cite this

@article{0e35234922d64389b0c6b8a21f8241dc,

title = "LIMIT CYCLE-FREE 2-D SEPARABLE DENOMINATOR DIGITAL FILTERS UNDER ANY CONSTANT INPUT CONDITIONS.",

abstract = "In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero input limit cycles.",

author = "Masayuki Kawamata and Tatsuo Higuchi",

year = "1987",

month = apr,

day = "1",

language = "English",

volume = "E70",

pages = "373--375",

journal = "Transactions of the Institute of Electronics, Information and Communication Engineers, Section E (",

number = "4",

}

TY - JOUR

T1 - LIMIT CYCLE-FREE 2-D SEPARABLE DENOMINATOR DIGITAL FILTERS UNDER ANY CONSTANT INPUT CONDITIONS.

AU - Kawamata, Masayuki

AU - Higuchi, Tatsuo

PY - 1987/4/1

Y1 - 1987/4/1

N2 - In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero input limit cycles.

AB - In order to suppress constant input limit cycles in 2-D separable denominator digital filters, bias cancel realizations are proposed by modifying 2-D separable denominator digital filters free of zero input limit cycles.

UR - http://www.scopus.com/inward/record.url?scp=0023329587&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023329587&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0023329587

VL - E70

SP - 373

EP - 375

JO - Transactions of the Institute of Electronics, Information and Communication Engineers, Section E (

JF - Transactions of the Institute of Electronics, Information and Communication Engineers, Section E (

IS - 4

ER -

LIMIT CYCLE-FREE 2-D SEPARABLE DENOMINATOR DIGITAL FILTERS UNDER ANY CONSTANT INPUT CONDITIONS.

Abstract

ASJC Scopus subject areas

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