Latchup Performance of Retrograde and Conventional n-Well CMOS Technologies

Alan G. Lewis; Russel A. Martin; Tiao Yuan Huang; John Y. Chen; Mitsumasa Koyanagi

doi:10.1109/T-ED.1987.23211

Latchup Performance of Retrograde and Conventional n-Well CMOS Technologies

Alan G. Lewis, Russel A. Martin, Tiao Yuan Huang, John Y. Chen, Mitsumasa Koyanagi

New Industry Creation Hatchery Center (NICHe)

Research output: Contribution to journal › Article › peer-review

40 Citations (Scopus)

Abstract

The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+ epitaxial material.

Original language	English
Pages (from-to)	2156-2164
Number of pages	9
Journal	IEEE Transactions on Electron Devices
Volume	34
Issue number	10
DOIs	https://doi.org/10.1109/T-ED.1987.23211
Publication status	Published - 1987 Oct

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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abstract = "The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+ epitaxial material.",

author = "Lewis, {Alan G.} and Martin, {Russel A.} and Huang, {Tiao Yuan} and Chen, {John Y.} and Mitsumasa Koyanagi",

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AB - The static and transient latchup performance of conventional and retrograde n-well CMOS technologies is compared. The retrograde n-well structures are shown to have superior latchup immunity, due primarily to the reduced n-well sheet resistance and the greater tolerance to thin p on p+ epitaxial material.

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Latchup Performance of Retrograde and Conventional n-Well CMOS Technologies

Abstract

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