Key technologies for 500-MHz VLSI system ultimate

Teruo Tamama, Naoaki Narumi, Tai ichi Otsuji, Masao Suzuki, Tsuneta Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Technologies needed for constructing ULTIMATE, including an 8-ps-resolution timing generator, a formatter with a real-time waveform control function, a 2.5-ps-resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector are described. Almost all the pin-electronics hardware has been integrated on twelve kinds of LSIs, eight of which are 2.5K-gate and 400-gate ultrahigh- speed bipolar gate arrays. ULTIMATE realizes ±55-ps overall timing accuracy by the timing calibration method which combines a standard comparator-based method and a TDR (time-domain reflectometry)-based method.

Original languageEnglish
Title of host publicationDigest of Papers - International Test Conference
PublisherPubl by IEEE
Pages108-113
Number of pages6
ISBN (Print)0818608706
Publication statusPublished - 1988 Dec 1
Externally publishedYes

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

ASJC Scopus subject areas

  • Engineering(all)

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