INVESTIGATION AND REDUCTION OF HOT ELECTRON INDUCED PUNCHTHROUGH (HEIP) EFFECT IN SUBMICRON PMOSFETS.

M. Koyanagi; A. G. Lewis; J. Zhu; R. A. Martin; T. Y. Huang; J. Y. Chen

doi:10.1109/iedm.1986.191295

INVESTIGATION AND REDUCTION OF HOT ELECTRON INDUCED PUNCHTHROUGH (HEIP) EFFECT IN SUBMICRON PMOSFETS.

M. Koyanagi, A. G. Lewis, J. Zhu, R. A. Martin, T. Y. Huang, J. Y. Chen

New Industry Creation Hatchery Center (NICHe)

Research output: Contribution to journal › Conference article

38 Citations (Scopus)

Abstract

Hot carrier reliability in submicrometer PMOSFETs has been investigated. The punch-through voltage is seriously reduced due to hot electron induced punch-through (HEIP) in submicrometer PMOSFETs. In order to mitigate the HEIP effect, a lightly doped drain (LDD) PMOSFET has been optimized by examining the channel electric field, substrate and gate currents, and the threshold voltage shifts due to hot electron injection. A device lifetime of more than 10 years has been obtained using LDD PMOSFETs with gate lengths of 0. 8 mu m at the worst case supply voltage (5. 5 V).

Original language	English
Pages (from-to)	722-725
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/iedm.1986.191295
Publication status	Published - 1986 Jan 1

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/iedm.1986.191295

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Koyanagi, M., Lewis, A. G., Zhu, J., Martin, R. A., Huang, T. Y., & Chen, J. Y. (1986). INVESTIGATION AND REDUCTION OF HOT ELECTRON INDUCED PUNCHTHROUGH (HEIP) EFFECT IN SUBMICRON PMOSFETS. Technical Digest - International Electron Devices Meeting, 722-725. https://doi.org/10.1109/iedm.1986.191295

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abstract = "Hot carrier reliability in submicrometer PMOSFETs has been investigated. The punch-through voltage is seriously reduced due to hot electron induced punch-through (HEIP) in submicrometer PMOSFETs. In order to mitigate the HEIP effect, a lightly doped drain (LDD) PMOSFET has been optimized by examining the channel electric field, substrate and gate currents, and the threshold voltage shifts due to hot electron injection. A device lifetime of more than 10 years has been obtained using LDD PMOSFETs with gate lengths of 0. 8 mu m at the worst case supply voltage (5. 5 V).",

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AU - Martin, R. A.

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