Introduction of atomically flattening of Si surface to large-scale integration process employing shallow trench isolation

Tetsuya Goto, Rihito Kuroda, Naoya Akagawa, Tomoyuki Suwa, Akinobu Teramoto, Xiang Li, Toshiki Obara, Daiki Kimoto, Shigetoshi Sugawa, Yutaka Kamata, Yuki Kumagai, Katsuhiko Shibusawa

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

Atomically flattening technology was introduced to the widely used complementary metal oxide silicon process employing sallow trench isolation at the 0.22-μm technology node. Two methods were investigated. The first method is to apply the atomically flattening to the starting Si wafer, and the second method is to apply this just before forming the gate oxide. In both methods, atomically flat gate insulator/Si interface could be obtained, and the test array circuit for evaluating the electrical characteristics of many (>130,000) metal oxide semiconductor field effect transistors was successfully fabricated on an entire 200-mm-diameter wafer. By evaluating the test circuit, the noise amplitude of the gate-source voltage related to the random telegraph noise was reduced owing to introducing the atomically flat gate insulator/Si interface. The charge-to-breakdown of the gate oxide was also improved.

Original languageEnglish
Pages (from-to)P67-P72
JournalECS Journal of Solid State Science and Technology
Volume5
Issue number2
DOIs
Publication statusPublished - 2016

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials

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