Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs

Takashi Hashimoto; Takahiro Kumauchi; Tomoko Jinbo; Kunihiko Watanabe; Eiichi Yoshida; Hideo Miura; Takeo Shiba; Yoichi Tamaki

Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs

Takashi Hashimoto, Takahiro Kumauchi, Tomoko Jinbo, Kunihiko Watanabe, Eiichi Yoshida, Hideo Miura, Takeo Shiba, Yoichi Tamaki

Research output: Contribution to conference › Paper › peer-review

2 Citations (Scopus)

Abstract

The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affect a lot on crystallization process of amorphous-silicon to polysilicon, which results in a changes of stress at the emitter layer.

Original language	English
Pages	181-184
Number of pages	4
Publication status	Published - 1996 Dec 1
Externally published	Yes
Event	Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA Duration: 1996 Sep 29 → 1996 Oct 1

Other

Other	Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
City	Minneapolis, MN, USA
Period	96/9/29 → 96/10/1

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs. / Hashimoto, Takashi; Kumauchi, Takahiro; Jinbo, Tomoko; Watanabe, Kunihiko; Yoshida, Eiichi; Miura, Hideo; Shiba, Takeo; Tamaki, Yoichi.

1996. 181-184 Paper presented at Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, USA, .

Research output: Contribution to conference › Paper › peer-review

@conference{34973ccef35e4e8cb2b74974ab8a4a8f,

title = "Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs",

abstract = "The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affect a lot on crystallization process of amorphous-silicon to polysilicon, which results in a changes of stress at the emitter layer.",

author = "Takashi Hashimoto and Takahiro Kumauchi and Tomoko Jinbo and Kunihiko Watanabe and Eiichi Yoshida and Hideo Miura and Takeo Shiba and Yoichi Tamaki",

year = "1996",

month = dec,

day = "1",

language = "English",

pages = "181--184",

note = "Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting ; Conference date: 29-09-1996 Through 01-10-1996",

}

TY - CONF

T1 - Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs

AU - Hashimoto, Takashi

AU - Kumauchi, Takahiro

AU - Jinbo, Tomoko

AU - Watanabe, Kunihiko

AU - Yoshida, Eiichi

AU - Miura, Hideo

AU - Shiba, Takeo

AU - Tamaki, Yoichi

PY - 1996/12/1

Y1 - 1996/12/1

N2 - The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affect a lot on crystallization process of amorphous-silicon to polysilicon, which results in a changes of stress at the emitter layer.

AB - The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affect a lot on crystallization process of amorphous-silicon to polysilicon, which results in a changes of stress at the emitter layer.

UR - http://www.scopus.com/inward/record.url?scp=0030385448&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030385448&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0030385448

SP - 181

EP - 184

T2 - Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Y2 - 29 September 1996 through 1 October 1996

ER -

Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs

Abstract

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ASJC Scopus subject areas

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