Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs

Takashi Hashimoto, Takahiro Kumauchi, Tomoko Jinbo, Kunihiko Watanabe, Eiichi Yoshida, Hideo Miura, Takeo Shiba, Yoichi Tamaki

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affect a lot on crystallization process of amorphous-silicon to polysilicon, which results in a changes of stress at the emitter layer.

Original languageEnglish
Pages181-184
Number of pages4
Publication statusPublished - 1996 Dec 1
Externally publishedYes
EventProceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
Duration: 1996 Sep 291996 Oct 1

Other

OtherProceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
CityMinneapolis, MN, USA
Period96/9/2996/10/1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Hashimoto, T., Kumauchi, T., Jinbo, T., Watanabe, K., Yoshida, E., Miura, H., Shiba, T., & Tamaki, Y. (1996). Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs. 181-184. Paper presented at Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, USA, .