Abstract
The in-situ phosphorus-doped polysilicon (IDP) emitter technique has been developed to form narrow and flat emitter region. One major problem to form the IDP process was found to be hFE fluctuation control. We revealed the cause and mechanism of the hFE variation and indicated the effective method of improving the device characteristics. It is concluded that the polySi/Si interface condition affect a lot on crystallization process of amorphous-silicon to polysilicon, which results in a changes of stress at the emitter layer.
| Original language | English |
|---|---|
| Pages | 181-184 |
| Number of pages | 4 |
| Publication status | Published - 1996 Dec 1 |
| Externally published | Yes |
| Event | Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA Duration: 1996 Sep 29 → 1996 Oct 1 |
Other
| Other | Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting |
|---|---|
| City | Minneapolis, MN, USA |
| Period | 96/9/29 → 96/10/1 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Cite this
Hashimoto, T., Kumauchi, T., Jinbo, T., Watanabe, K., Yoshida, E., Miura, H., Shiba, T., & Tamaki, Y. (1996). Interface controlled IDP process technology for 0.3 μm high-speed bipolar and BiCMOS LSIs. 181-184. Paper presented at Proceedings of the 1996 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, MN, USA, .