Efficient image processing from a low level to a higher level on a PSM system is described. PSM is a multiprocessor system architecture with pipelined multiple-instruction multiple-data (MIMD) processors, shared memory, and a multistage interconnection network designed for high-speed parallel image processing. A parallel image processor, PSM-32, which is being constructed based on the PSM architecture, is discussed. To ensure total efficient instruction and data flows in the presence of the memory access delays commonly occurring on a multistage interconnection network machine, an architecture with a pipelined MIMD processor is proposed for the PSM system.
|Number of pages||3|
|Journal||Proceedings - International Conference on Pattern Recognition|
|Publication status||Published - 1990 Dec 1|
|Event||Proceedings of the 10th International Conference on Pattern Recognition - Atlantic City, NJ, USA|
Duration: 1990 Jun 16 → 1990 Jun 21
ASJC Scopus subject areas
- Computer Vision and Pattern Recognition