The decreased feature size of metal-oxide-semiconductor (MOS) devices in ultra-large-scale-integrated circuits (ULSIs) requires the nano-scale complementary MOS (CMOS) fabrication technology. As silicon devices are scaled down to the nanometer regime, the device technology is facing to several difficulties. Standby power consumption in CMOS devices is now one of the most serious problem and becoming a limiting factor in MOSFET scaling . Short channel effects (SCEs) such as threshold voltage (Vth ) roll off and sub-threshold slope (S-factor) degradation causes significant increased in power consumption. Catastrophic increase in static power consumption due to shot channel effects (SCEs) becomes the serious problem in future VLSI circuits. Especially, the leakage current in the SRAM array is the most critical issue for a low-power SoC because it occupies the considerable part of LSIs.