Three-dimensional (3D) integration of silicon microelectronic devices improves the electronic functions of devices and minimizes packaging density drastically. A through-silicon via (TSV) structure is indispensable for maximizing the density of interconnections among the stacked silicon chips. However, since the TSV structure is surrounded by silicon, and there is large mismatch in materials properties between metallic materials used for the TSV structure and silicon, thermal stress is essentially generated around the TSV structure during their fabrication process and operating conditions. Recently, electroplated copper thin films have started to be applied to the interconnection material in the TSV structure because of its low electric resistivity and high thermal conductivity. However, the electrical resistivity of the electroplated copper thin films surrounded by SiO2 was found to vary drastically comparing with those of the conventional bulk material. This was because that the electroplated copper thin films consisted of grains with low crystallinity and grain boundaries, in other words, abnormally high defect density. Thus, both the crystallinity and electrical properties of the TSV structure was investigated quantitatively by changing their electroplating conditions and thermal history after the electroplating. It was observed that many voids and hillocks appeared in the TSV structures depending on the electroplating conditions. It was also found that the stress-induced migration occurred after the high temperature annealing which was introduced for improving the crystallinity of the electroplated films. Therefore, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplating to assure both the mechanical and electrical properties of the films.