Improvement of interfacial properties with interfacial layer in La2O3/Ge structure

J. Song; K. Kakushima; P. Ahmet; K. Tsutsui; N. Sugii; T. Hattori; H. Iwai

doi:10.1016/j.mee.2007.04.107

Improvement of interfacial properties with interfacial layer in La₂O₃/Ge structure

J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai

Research output: Contribution to journal › Article › peer-review

37 Citations (Scopus)

Abstract

The electrical characteristics and interfacial properties of La₂O₃/Ge structures under various post-deposition annealing (PDA) conditions are studied. We found that the interfacial Ge oxide layer reduced the D_it, while redundant growth of the oxide led to increment of CET. In order to satisfy small CET and low D_it, appropriate interfacial layer (IL) thickness is assumed to be 1.0-1.5 nm. On the other hand, Ge sub-oxide in the IL caused to increase hysteresis. Instead, by introducing the Ge chemical oxide, an interfacial La-germanate layer formed with PDA at 500 °C in N₂, which could reduced both the hysteresis and D_it.

Original language	English
Pages (from-to)	2336-2339
Number of pages	4
Journal	Microelectronic Engineering
Volume	84
Issue number	9-10
DOIs	https://doi.org/10.1016/j.mee.2007.04.107
Publication status	Published - 2007 Sep
Externally published	Yes

Keywords

Germanate
Germanium
High-k
Interface trap density
LaO
Lanthanum oxide
PDA

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Condensed Matter Physics
Surfaces, Coatings and Films
Electrical and Electronic Engineering

Access to Document

10.1016/j.mee.2007.04.107

Cite this

@article{9d7915997ce04bdbb81fb1bf62cc2b87,

title = "Improvement of interfacial properties with interfacial layer in La2O3/Ge structure",

abstract = "The electrical characteristics and interfacial properties of La2O3/Ge structures under various post-deposition annealing (PDA) conditions are studied. We found that the interfacial Ge oxide layer reduced the Dit, while redundant growth of the oxide led to increment of CET. In order to satisfy small CET and low Dit, appropriate interfacial layer (IL) thickness is assumed to be 1.0-1.5 nm. On the other hand, Ge sub-oxide in the IL caused to increase hysteresis. Instead, by introducing the Ge chemical oxide, an interfacial La-germanate layer formed with PDA at 500 °C in N2, which could reduced both the hysteresis and Dit.",

keywords = "Germanate, Germanium, High-k, Interface trap density, LaO, Lanthanum oxide, PDA",

author = "J. Song and K. Kakushima and P. Ahmet and K. Tsutsui and N. Sugii and T. Hattori and H. Iwai",

note = "Funding Information: This work was partially supported by Semiconductor Technology Academic Research Center (STARC).",

year = "2007",

month = sep,

doi = "10.1016/j.mee.2007.04.107",

language = "English",

volume = "84",

pages = "2336--2339",

journal = "Microelectronic Engineering",

issn = "0167-9317",

publisher = "Elsevier",

number = "9-10",

}

TY - JOUR

T1 - Improvement of interfacial properties with interfacial layer in La2O3/Ge structure

AU - Song, J.

AU - Kakushima, K.

AU - Ahmet, P.

AU - Tsutsui, K.

AU - Sugii, N.

AU - Hattori, T.

AU - Iwai, H.

N1 - Funding Information: This work was partially supported by Semiconductor Technology Academic Research Center (STARC).

PY - 2007/9

Y1 - 2007/9

N2 - The electrical characteristics and interfacial properties of La2O3/Ge structures under various post-deposition annealing (PDA) conditions are studied. We found that the interfacial Ge oxide layer reduced the Dit, while redundant growth of the oxide led to increment of CET. In order to satisfy small CET and low Dit, appropriate interfacial layer (IL) thickness is assumed to be 1.0-1.5 nm. On the other hand, Ge sub-oxide in the IL caused to increase hysteresis. Instead, by introducing the Ge chemical oxide, an interfacial La-germanate layer formed with PDA at 500 °C in N2, which could reduced both the hysteresis and Dit.

AB - The electrical characteristics and interfacial properties of La2O3/Ge structures under various post-deposition annealing (PDA) conditions are studied. We found that the interfacial Ge oxide layer reduced the Dit, while redundant growth of the oxide led to increment of CET. In order to satisfy small CET and low Dit, appropriate interfacial layer (IL) thickness is assumed to be 1.0-1.5 nm. On the other hand, Ge sub-oxide in the IL caused to increase hysteresis. Instead, by introducing the Ge chemical oxide, an interfacial La-germanate layer formed with PDA at 500 °C in N2, which could reduced both the hysteresis and Dit.

KW - Germanate

KW - Germanium

KW - High-k

KW - Interface trap density

KW - LaO

KW - Lanthanum oxide

KW - PDA

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JO - Microelectronic Engineering

JF - Microelectronic Engineering

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