Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure

M. Kadoshima, T. Matsuki, N. Mise, M. Sato, M. Hayashi, T. Aminaka, E. Kurosawa, M. Kitajima, S. Miyazaki, K. Shiraishi, T. Chikyo, K. Yamada, T. Aoyama, Y. Nara, Y. Ohji

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (∼2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (∼10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.

Original languageEnglish
Title of host publication2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages48-49
Number of pages2
DOIs
Publication statusPublished - 2008 Sep 23
Externally publishedYes
Event2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States
Duration: 2008 Jun 172008 Jun 19

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
CountryUnited States
CityHonolulu, HI
Period08/6/1708/6/19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure'. Together they form a unique fingerprint.

  • Cite this

    Kadoshima, M., Matsuki, T., Mise, N., Sato, M., Hayashi, M., Aminaka, T., Kurosawa, E., Kitajima, M., Miyazaki, S., Shiraishi, K., Chikyo, T., Yamada, K., Aoyama, T., Nara, Y., & Ohji, Y. (2008). Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure. In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT (pp. 48-49). [4588559] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588559