TY - GEN
T1 - Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure
AU - Kadoshima, M.
AU - Matsuki, T.
AU - Mise, N.
AU - Sato, M.
AU - Hayashi, M.
AU - Aminaka, T.
AU - Kurosawa, E.
AU - Kitajima, M.
AU - Miyazaki, S.
AU - Shiraishi, K.
AU - Chikyo, T.
AU - Yamada, K.
AU - Aoyama, T.
AU - Nara, Y.
AU - Ohji, Y.
PY - 2008/9/23
Y1 - 2008/9/23
N2 - A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (∼2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (∼10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.
AB - A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (∼2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (∼10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.
UR - http://www.scopus.com/inward/record.url?scp=51949086028&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51949086028&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2008.4588559
DO - 10.1109/VLSIT.2008.4588559
M3 - Conference contribution
AN - SCOPUS:51949086028
SN - 9781424418053
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 48
EP - 49
BT - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
T2 - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Y2 - 17 June 2008 through 19 June 2008
ER -