Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure

M. Kadoshima; T. Matsuki; N. Mise; M. Sato; M. Hayashi; T. Aminaka; E. Kurosawa; M. Kitajima; S. Miyazaki; K. Shiraishi; T. Chikyo; K. Yamada; T. Aoyama; Y. Nara; Y. Ohji

doi:10.1109/VLSIT.2008.4588559

Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure

M. Kadoshima, T. Matsuki, N. Mise, M. Sato, M. Hayashi, T. Aminaka, E. Kurosawa, M. Kitajima, S. Miyazaki, K. Shiraishi, T. Chikyo, K. Yamada, T. Aoyama, Y. Nara, Y. Ohji

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-R_s(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (∼2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (∼10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.

Original language	English
Title of host publication	2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages	48-49
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2008.4588559
Publication status	Published - 2008 Sep 23
Externally published	Yes
Event	2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States Duration: 2008 Jun 17 → 2008 Jun 19

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Country	United States
City	Honolulu, HI
Period	08/6/17 → 08/6/19

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/VLSIT.2008.4588559

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Kadoshima, M., Matsuki, T., Mise, N., Sato, M., Hayashi, M., Aminaka, T., Kurosawa, E., Kitajima, M., Miyazaki, S., Shiraishi, K., Chikyo, T., Yamada, K., Aoyama, T., Nara, Y., & Ohji, Y. (2008). Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure. In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT (pp. 48-49). [4588559] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588559

Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure. / Kadoshima, M.; Matsuki, T.; Mise, N.; Sato, M.; Hayashi, M.; Aminaka, T.; Kurosawa, E.; Kitajima, M.; Miyazaki, S.; Shiraishi, K.; Chikyo, T.; Yamada, K.; Aoyama, T.; Nara, Y.; Ohji, Y.

2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 48-49 4588559 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kadoshima, M, Matsuki, T, Mise, N, Sato, M, Hayashi, M, Aminaka, T, Kurosawa, E, Kitajima, M, Miyazaki, S, Shiraishi, K, Chikyo, T, Yamada, K, Aoyama, T, Nara, Y & Ohji, Y 2008, Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure. in 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT., 4588559, Digest of Technical Papers - Symposium on VLSI Technology, pp. 48-49, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, Honolulu, HI, United States, 08/6/17. https://doi.org/10.1109/VLSIT.2008.4588559

Kadoshima M, Matsuki T, Mise N, Sato M, Hayashi M, Aminaka T et al. Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure. In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 48-49. 4588559. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588559

Kadoshima, M. ; Matsuki, T. ; Mise, N. ; Sato, M. ; Hayashi, M. ; Aminaka, T. ; Kurosawa, E. ; Kitajima, M. ; Miyazaki, S. ; Shiraishi, K. ; Chikyo, T. ; Yamada, K. ; Aoyama, T. ; Nara, Y. ; Ohji, Y. / Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure. 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. pp. 48-49 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (∼2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (∼10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.",

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Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure

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