Implementation of a multi-context FPGA based on flexible-context- partitioning

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. Proposed MC-FPGA uses same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. We also propose an asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts. The proposed architecture is designed using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Pages201-207
Number of pages7
Publication statusPublished - 2008 Dec 1
Event2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States
Duration: 2008 Jul 142008 Jul 17

Other

Other2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
CountryUnited States
CityLas Vegas, NV
Period08/7/1408/7/17

Keywords

  • Asynchronous FPGA
  • DPGA
  • Multi-context

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software

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