Implementation of a large scale hardware neural network system Based on stochastic logic

Akiyoshi Momoi, Shunsuke Akimoto, Shigeo Sato, Koji Nakajima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, we present a large scale hardware neural network system which consists of 16 chips, 1024 neurons. The system is realized by using stochastic logic. Stochastic logic makes possible to implement numerous neurons on a VLSI chip and to build a system comprising multiple chips easily. In addition, stochastic logic has a characteristic as some noise is generated while coding operations. This noise is effective for escaping from the local minima in a Hopfield network. The availability of this noise is confirmed in the measurement of our system.

Original languageEnglish
Title of host publication2004 IEEE International Joint Conference on Neural Networks - Proceedings
Pages2671-2675
Number of pages5
DOIs
Publication statusPublished - 2004
Event2004 IEEE International Joint Conference on Neural Networks - Proceedings - Budapest, Hungary
Duration: 2004 Jul 252004 Jul 29

Publication series

NameIEEE International Conference on Neural Networks - Conference Proceedings
Volume4
ISSN (Print)1098-7576

Other

Other2004 IEEE International Joint Conference on Neural Networks - Proceedings
CountryHungary
CityBudapest
Period04/7/2504/7/29

ASJC Scopus subject areas

  • Software

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