Implementation of a high-speed asynchronous data-transfer chip based on multiple-valued current-signal multiplexing

Tomohiro Takahashi, Takahiro Hanyu

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

This paper presents an asynchronous multiple-valued current-mode data-transfer controller chip based on a 1-phase dual-rail encoding technique. The proposed encoding technique enables "one-way delay" asynchronous data transfer because request and acknowledge signals can be transmitted simultaneously and valid states are detected by calculating the sum of dual-rail codewords. Since a key component, a current-to-voltage conversion circuit in a valid-state detector, is tuned so as to obtain a sufficient voltage range to improve switching speed of a comparator, signal detection can be performed quickly in spite of using 6-level signals. It is evaluated using HSPICE simulation with a 0.18-μm CMOS that the throughput of the proposed circuit based on the 1-phase dual-rail scheme attains 435 Mbps/wire which is 2.9 times faster than that of a CMOS circuit based on a conventional 4-phase dual-rail scheme. The test chip is fabricated, and the asynchronous data-transfer behavior of the proposed scheme is confirmed.

Original languageEnglish
Pages (from-to)1598-1604
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE89-C
Issue number11
DOIs
Publication statusPublished - 2006 Nov

Keywords

  • Delay-insensitive
  • Dual-rail encoding
  • Globally asynchronous locally synchronous (GALS)
  • Network-on-chip (NoC)
  • Point-to-point communication

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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