Implementation of a high performance LSI for inverse kinematics computation

Michitaka Kameyama; Takao Matsumoto; Hideki Egami; Tatsuo Higuchi

Implementation of a high performance LSI for inverse kinematics computation

Michitaka Kameyama, Takao Matsumoto, Hideki Egami, Tatsuo Higuchi

Research output: Contribution to journal › Conference article › peer-review

Abstract

The authors present an LSI (large-scale integrated) circuit for high-speed inverse kinematics computation. They demonstrate that inverse kinematic solutions can be described by two-dimensional vector rotations and arc tangent operations, and that these operations can be efficiently computed by the coordinate rotation digital computer (CORDIC) algorithms. The chip is fabricated using 1.5-μm CMOS gate array technology, and the design of the arithmetic unit on the chip is based on the CORDIC algorithms. Pipelining is fully used in the processor to enhance the operating ratio up to 100%. The resulting compact inverse kinematics processor is composed of the above chip and a few memory chips for program and data. The processor can be used for various kinds of manipulators.

Original language	English
Pages (from-to)	757-762
Number of pages	6
Journal	Proceedings - IEEE International Conference on Robotics and Automation
Publication status	Published - 1989
Externally published	Yes
Event	1989 IEEE International Conference on Robotics and Automation, ICRA 1989 - Scottsdale, AZ, USA Duration: 1989 May 14 → 1989 May 19

ASJC Scopus subject areas

Software
Control and Systems Engineering
Artificial Intelligence
Electrical and Electronic Engineering

Cite this

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title = "Implementation of a high performance LSI for inverse kinematics computation",

abstract = "The authors present an LSI (large-scale integrated) circuit for high-speed inverse kinematics computation. They demonstrate that inverse kinematic solutions can be described by two-dimensional vector rotations and arc tangent operations, and that these operations can be efficiently computed by the coordinate rotation digital computer (CORDIC) algorithms. The chip is fabricated using 1.5-μm CMOS gate array technology, and the design of the arithmetic unit on the chip is based on the CORDIC algorithms. Pipelining is fully used in the processor to enhance the operating ratio up to 100%. The resulting compact inverse kinematics processor is composed of the above chip and a few memory chips for program and data. The processor can be used for various kinds of manipulators.",

author = "Michitaka Kameyama and Takao Matsumoto and Hideki Egami and Tatsuo Higuchi",

year = "1989",

language = "English",

pages = "757--762",

journal = "Proceedings - IEEE International Conference on Robotics and Automation",

issn = "1050-4729",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "1989 IEEE International Conference on Robotics and Automation, ICRA 1989 ; Conference date: 14-05-1989 Through 19-05-1989",

}

TY - JOUR

T1 - Implementation of a high performance LSI for inverse kinematics computation

AU - Kameyama, Michitaka

AU - Matsumoto, Takao

AU - Egami, Hideki

AU - Higuchi, Tatsuo

PY - 1989

Y1 - 1989

N2 - The authors present an LSI (large-scale integrated) circuit for high-speed inverse kinematics computation. They demonstrate that inverse kinematic solutions can be described by two-dimensional vector rotations and arc tangent operations, and that these operations can be efficiently computed by the coordinate rotation digital computer (CORDIC) algorithms. The chip is fabricated using 1.5-μm CMOS gate array technology, and the design of the arithmetic unit on the chip is based on the CORDIC algorithms. Pipelining is fully used in the processor to enhance the operating ratio up to 100%. The resulting compact inverse kinematics processor is composed of the above chip and a few memory chips for program and data. The processor can be used for various kinds of manipulators.

AB - The authors present an LSI (large-scale integrated) circuit for high-speed inverse kinematics computation. They demonstrate that inverse kinematic solutions can be described by two-dimensional vector rotations and arc tangent operations, and that these operations can be efficiently computed by the coordinate rotation digital computer (CORDIC) algorithms. The chip is fabricated using 1.5-μm CMOS gate array technology, and the design of the arithmetic unit on the chip is based on the CORDIC algorithms. Pipelining is fully used in the processor to enhance the operating ratio up to 100%. The resulting compact inverse kinematics processor is composed of the above chip and a few memory chips for program and data. The processor can be used for various kinds of manipulators.

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M3 - Conference article

AN - SCOPUS:0024863320

SP - 757

EP - 762

JO - Proceedings - IEEE International Conference on Robotics and Automation

JF - Proceedings - IEEE International Conference on Robotics and Automation

SN - 1050-4729

T2 - 1989 IEEE International Conference on Robotics and Automation, ICRA 1989

Y2 - 14 May 1989 through 19 May 1989

ER -

Implementation of a high performance LSI for inverse kinematics computation

Abstract

ASJC Scopus subject areas

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