Implementation of a DRAM-cell-based multiple-valued logic-in-memory circuit

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-μm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.

Original languageEnglish
Pages (from-to)1814-1823
Number of pages10
JournalIEICE Transactions on Electronics
VolumeE85-C
Issue number10
Publication statusPublished - 2002 Oct

Keywords

  • Content-addressable memory
  • Functional pass-gate
  • Interconnection problem
  • Multiple-valued logic
  • Pass-transistor network

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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