TY - JOUR
T1 - Implementation of a class of asymmetrical neural networks with application to an a‐d converter
AU - Sato, Shigeo
AU - Nishimura, Toshihiko
AU - Murota, Junichi
AU - Nakajima, Koji
AU - Sawada, Yasuji
PY - 1992/1/1
Y1 - 1992/1/1
N2 - This paper attempts to clarify the problems which occur in implementation of a large‐scale neural network. First, a neural A‐D converter with CMOS circuits is designed. Asymmetrical synaptic weights were used to avoid the local minima problem for a neural A‐D converter. Furthermore, a chip is fabricated using 4 μm CMOS technology. Its successful action as an A‐D converter is verified and some possible causes of misoperation of the present circuit are presented.
AB - This paper attempts to clarify the problems which occur in implementation of a large‐scale neural network. First, a neural A‐D converter with CMOS circuits is designed. Asymmetrical synaptic weights were used to avoid the local minima problem for a neural A‐D converter. Furthermore, a chip is fabricated using 4 μm CMOS technology. Its successful action as an A‐D converter is verified and some possible causes of misoperation of the present circuit are presented.
KW - Periodic waveguide
KW - dielectric loaded waveguide
KW - finite element method
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U2 - 10.1002/ecjb.4420750711
DO - 10.1002/ecjb.4420750711
M3 - Article
AN - SCOPUS:0026889004
VL - 75
SP - 92
EP - 102
JO - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
SN - 8756-663X
IS - 7
ER -