This paper describes a design of a fine-grain Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) based on Multiple-Valued Source-Coupled Logic (MVSCL). An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 2-variable binary logic operation is realized using threshold logic gates. Using 0.35μm standard CMOS design rule, a bit-serial adder is designed using the MV-FPVLSI. Using HSPICE simulation tools, a cell is evaluated and compared with corresponding binary implementation. Comparison results show that, under normalized power consumption better performance can be achieved if the linear summation with weight 1 of the input currents is possible. Moreover, the area of a cell can be reduced to 24% without any degradation in performance. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.
|Number of pages||6|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2005 Sep 20|
|Event||35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada|
Duration: 2005 May 19 → 2005 May 21
ASJC Scopus subject areas
- Computer Science(all)