Abstract
The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ∼ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.
Original language | English |
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Title of host publication | 2014 IEEE International Reliability Physics Symposium, IRPS 2014 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Print) | 9781479933167 |
DOIs | |
Publication status | Published - 2014 Jan 1 |
Event | 52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United States Duration: 2014 Jun 1 → 2014 Jun 5 |
Other
Other | 52nd IEEE International Reliability Physics Symposium, IRPS 2014 |
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Country/Territory | United States |
City | Waikoloa, HI |
Period | 14/6/1 → 14/6/5 |
Keywords
- 3D DRAM
- Capacitance-time (C-t)
- charge carrier lifetime
- Cu diffusion
- Cu TSV
- retention time
ASJC Scopus subject areas
- Engineering(all)