Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

Kangwook Lee, Seiya Tanikawa, Hideki Naganuma, Jichoru Be, Mariappine Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-μm thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300°C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-μm ∼ 50-μm from arrays of 10-μm diameter Cu TSVs began to degrade after post-annealing at 300°C, 30 min owing to the in-sufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

Original languageEnglish
Title of host publication2014 IEEE International Reliability Physics Symposium, IRPS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479933167
DOIs
Publication statusPublished - 2014 Jan 1
Event52nd IEEE International Reliability Physics Symposium, IRPS 2014 - Waikoloa, HI, United States
Duration: 2014 Jun 12014 Jun 5

Other

Other52nd IEEE International Reliability Physics Symposium, IRPS 2014
CountryUnited States
CityWaikoloa, HI
Period14/6/114/6/5

Keywords

  • 3D DRAM
  • Capacitance-time (C-t)
  • charge carrier lifetime
  • Cu diffusion
  • Cu TSV
  • retention time

ASJC Scopus subject areas

  • Engineering(all)

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