Impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip for high-reliable 3-D DRAM

Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, Hideki Naganuma, Ji Choel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)

Abstract

The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40-μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30-μm thickness, but suddenly degraded below 20-μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300°C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300°C annealing.

Original languageEnglish
Article number6698353
Pages (from-to)379-385
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume61
Issue number2
DOIs
Publication statusPublished - 2014 Feb

Keywords

  • 3-D DRAM
  • Cu TSV
  • Cu diffusion
  • Extrinsic gettering
  • Mechanical strength
  • Retention time
  • Si Young's modulus

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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