TY - GEN
T1 - Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs
AU - Yoshida, Tomohiro
AU - Kobayashi, Kengo
AU - Otsuji, Taiichi
AU - Suemitsu, Tetsuya
N1 - Funding Information:
A part of this work was financially supported by the Research Institute of Electrical Communication (RIEC) of Tohoku University. The device fabrication was carried out at the Laboratory for Nanoelectronics and Spintronics at RIEC.
PY - 2013
Y1 - 2013
N2 - We report an impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs). Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different height in the stems of T-gates reveals that the parasitic gate delay decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more freedom to use the T-gate electrode with a large head in the devices for high-voltage applications.
AB - We report an impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs). Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different height in the stems of T-gates reveals that the parasitic gate delay decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more freedom to use the T-gate electrode with a large head in the devices for high-voltage applications.
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U2 - 10.1109/ESSDERC.2013.6818832
DO - 10.1109/ESSDERC.2013.6818832
M3 - Conference contribution
AN - SCOPUS:84902184799
SN - 9781479906499
T3 - European Solid-State Device Research Conference
SP - 115
EP - 118
BT - ESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference
PB - IEEE Computer Society
T2 - 43rd European Solid-State Device Research Conference, ESSDERC 2013
Y2 - 16 September 2013 through 20 September 2013
ER -