Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs

Tomohiro Yoshida, Kengo Kobayashi, Taiichi Otsuji, Tetsuya Suemitsu

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications.

Original languageEnglish
Pages (from-to)93-97
Number of pages5
JournalSolid-State Electronics
Publication statusPublished - 2014 Dec


  • Delay time analysis
  • HEMTs
  • InGaAs
  • T-gate

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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