A novel transistor with compact structures has been developed for future MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These excellent features are the result of its unique structure, that is responsible for the enlargement of gate-controllability to the channel and the electric field relaxation at the drain edge. As a result, this transistor will be suitable for future ULSI's.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering