Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

Yohei Sugawara; Hideto Hashiguchi; Seiya Tanikawa; Hisashi Kino; Kanuku Ri; Takafumi Fukusima; Mitsumasa Koyanagi; Tetsu Tanaka

doi:10.1109/ECTC.2015.7159687

Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

Yohei Sugawara, Hideto Hashiguchi, Seiya Tanikawa, Hisashi Kino, Kanuku Ri, Takafumi Fukusima, Mitsumasa Koyanagi, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.

Original language	English
Title of host publication	2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	822-827
Number of pages	6
ISBN (Electronic)	9781479986095
DOIs	https://doi.org/10.1109/ECTC.2015.7159687
Publication status	Published - 2015 Jul 15
Event	2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015 - San Diego, United States Duration: 2015 May 26 → 2015 May 29

Publication series

Name	Proceedings - Electronic Components and Technology Conference
Volume	2015-July
ISSN (Print)	0569-5503

Other

Other	2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015
Country/Territory	United States
City	San Diego
Period	15/5/26 → 15/5/29

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ECTC.2015.7159687

Cite this

Sugawara, Y., Hashiguchi, H., Tanikawa, S., Kino, H., Ri, K., Fukusima, T., Koyanagi, M., & Tanaka, T. (2015). Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV. In 2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015 (pp. 822-827). [7159687] (Proceedings - Electronic Components and Technology Conference; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2015.7159687

Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV. / Sugawara, Yohei; Hashiguchi, Hideto; Tanikawa, Seiya; Kino, Hisashi; Ri, Kanuku; Fukusima, Takafumi; Koyanagi, Mitsumasa; Tanaka, Tetsu.

2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 822-827 7159687 (Proceedings - Electronic Components and Technology Conference; Vol. 2015-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sugawara, Y, Hashiguchi, H, Tanikawa, S, Kino, H, Ri, K, Fukusima, T, Koyanagi, M & Tanaka, T 2015, Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV. in 2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015., 7159687, Proceedings - Electronic Components and Technology Conference, vol. 2015-July, Institute of Electrical and Electronics Engineers Inc., pp. 822-827, 2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015, San Diego, United States, 15/5/26. https://doi.org/10.1109/ECTC.2015.7159687

Sugawara Y, Hashiguchi H, Tanikawa S, Kino H, Ri K, Fukusima T et al. Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV. In 2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 822-827. 7159687. (Proceedings - Electronic Components and Technology Conference). https://doi.org/10.1109/ECTC.2015.7159687

Sugawara, Yohei ; Hashiguchi, Hideto ; Tanikawa, Seiya ; Kino, Hisashi ; Ri, Kanuku ; Fukusima, Takafumi ; Koyanagi, Mitsumasa ; Tanaka, Tetsu. / Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV. 2015 IEEE 65th Electronic Components and Technology Conference, ECTC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 822-827 (Proceedings - Electronic Components and Technology Conference).

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abstract = "3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.",

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AU - Ri, Kanuku

AU - Fukusima, Takafumi

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AB - 3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.

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Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

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