Abstract
3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.
Original language | English |
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Title of host publication | Proceedings - Electronic Components and Technology Conference |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 822-827 |
Number of pages | 6 |
Volume | 2015-July |
ISBN (Print) | 9781479986095 |
DOIs | |
Publication status | Published - 2015 Jul 15 |
Event | 2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015 - San Diego, United States Duration: 2015 May 26 → 2015 May 29 |
Other
Other | 2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015 |
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Country | United States |
City | San Diego |
Period | 15/5/26 → 15/5/29 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials