Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

Yohei Sugawara, Hideto Hashiguchi, Seiya Tanikawa, Hisashi Kino, Kang Wook Lee, Takafumi Fukusima, Mitsumasa Koyanagi, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.

Original languageEnglish
Title of host publicationProceedings - Electronic Components and Technology Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages822-827
Number of pages6
Volume2015-July
ISBN (Print)9781479986095
DOIs
Publication statusPublished - 2015 Jul 15
Event2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015 - San Diego, United States
Duration: 2015 May 262015 May 29

Other

Other2015 65th IEEE Electronic Components and Technology Conference, ECTC 2015
CountryUnited States
CitySan Diego
Period15/5/2615/5/29

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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